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LTC4156 1 4156f typical application features description dual-input power manager/ 3.5a lifepo 4 battery charger with i 2 c control and usb otg the lt c ? 4156 is a 15 watt i 2 c controlled power manager with powerpath? instant-on operation, high efficiency switching battery charging and usb compatibility. the LTC4156 seamlessly manages power distribution from two 5v sources , such as a usb port and a wall adapter, to a single-cell rechargeable lithium iron phosphate battery and a system load. the LTC4156s switching battery charger automatically limits its input current for usb compatibility, or may draw up to 3a from a high power wall adapter. the high efficiency step-down switching charger is designed to provide maximum power to the application and reduced heat in high power density applications. i 2 c adjustability of input current, charge current, battery float voltage, charge termination, and many other param- eters allows maximum flexibility. i 2 c status reporting of key system and charge parameters facilitates intelligent control decisions. usb on-the-go support provides 5v power back to the usb port without any additional com- ponents. a dual-input, priority multiplexing, overvoltage protection circuit guards the LTC4156 from high voltage damage on the v bus pin. the LTC4156 is available in the low profile (0.75mm) 28-lead 4mm 5mm qfn surface mount package. i 2 c controlled high power battery charger/usb power manager applications n high efficiency charger capable of 3.5a charge current n charge control algorithm specifically designed for lifepo 4 batteries (lithium iron phosphate) n monolithic switching regulator makes optimal use of limited power and thermal budget n dual input overvoltage protection controller n priority multiplexing for multiple inputs n i 2 c/smbus control and status feedback n ntc thermistor adc for temperature dependent charge algorithms ( jeita) n instant-on operation with low battery n battery ideal diode controller for power management n usb on-the-go power delivery to the usb port n four float voltage settings (3.45v, 3.55v, 3.6v, 3.8v) n 28- lead 4mm 5mm qfn package n portable medical devices n portable industrial devices n backup devices l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and powerpath and bat- track are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. v bus v in clprog1 clprog2 prog v c ovgcap irq i 2 c gnd 3 3.6k 100k id usbgt chgsns usbsns 1.21k 499 47nf 10f 22f ntc batsns batgate ntcbias wallgt LTC4156 wallsns v out sw to system load 1h 4156 ta01a load current (a) 0 0 efficiency (%) 10 30 40 50 100 70 1.0 2.0 2.5 4156 ta01b 20 80 90 60 0.5 1.5 3.0 v bat = 3.3v switching regulator efficiency www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 2 4156f table of contents features ............................................................................................................................ 1 applications ....................................................................................................................... 1 typical application ............................................................................................................... 1 description ......................................................................................................................... 1 absolute maximum ratings ..................................................................................................... 3 order information ................................................................................................................. 3 pin configuration ................................................................................................................. 3 electrical characteristics ........................................................................................................ 4 typical performance characteristics .......................................................................................... 9 pin functions ..................................................................................................................... 12 block diagram .................................................................................................................... 15 timing diagrams ................................................................................................................ 16 operation .......................................................................................................................... 17 i 2 c ........................................................................................................................................................................ 17 applications information ....................................................................................................... 40 typical applications ............................................................................................................. 47 package description ............................................................................................................ 51 typical application .............................................................................................................. 52 related parts ..................................................................................................................... 52 www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 3 4156f pin configuration absolute maximum ratings v bus ( transient ) t < 1 ms, duty cycle < 1% ... C0.3 v to 7 v v bus ( steady state ), batsns , irq , ntc ...... C0.3 v to 6 v dvcc , sda , scl ( note 3) ........................ C0.3 v to v max i wallsns , i usbsns ............................................... 20 ma i ntcbias , i irq .......................................................... 10 ma i sw , i vout , i chgsns ( both pins in each case ) .............. 4 a operating junction temperature range ... C40 c to 125 c storage temperature range .................. C65 c to 150 c (notes 1, 2) 9 10 top view 29 gnd ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 sda dvcc irq id clprog1 clprog2 wallsns usbsns v out v out chgsns chgsns prog batgate batsns ntc scl sw sw v bus v bus v bus usbgt ovgcap wallgt v c v outsns ntcbias 7 17 18 19 20 21 22 16 8 15 t jmax = 125c, v ja = 43c/w exposed pad (pin 29) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range LTC4156eufd#pbf LTC4156eufd#trpbf 4156 28-lead (4mm 5mm 0.75mm) plastic qfn C40c to 125c LTC4156iufd#pbf LTC4156iufd#trpbf 4156 28-lead (4mm 5mm 0.75mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 4 4156f the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a t j = 25c (note 2). v bus = 5v, batsns = 3.3v, dvcc = 3.3v, r clprog1 = r clprog2 = 1.21k, r prog = 499, unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units switching battery charger v bus input supply voltage l 4.35 5.5 v v busreg undervoltage current reduction input undervoltage current limit enabled 4.30 v i vbusq input quiescent current usb suspend mode 100ma i vbus mode, i vout = 0a, charger off 500ma C 3a i vbus modes, i vout = 0a, charger off clprog1 mode, i vout = 0a, charger off 0.060 0.560 17 17 ma ma ma ma i batq battery drain current v bus > v uvlo , battery charger off , i vout = 0a v bus = 0v, i vout = 0a storage and shipment mode, dvcc = 0v 7.0 2.0 0.6 3.0 1.25 a a a i vbuslim total input current when load exceeds power limit 100ma i vbus mode (usb lo power) (default) 500ma i vbus mode (usb hi power) 600ma i vbus mode 700ma i vbus mode 800ma i vbus mode 900ma i vbus mode (usb 3.0) 1.00a i vbus mode 1.25a i vbus mode 1.50a i vbus mode 1.75a i vbus mode 2.00a i vbus mode 2.25a i vbus mode 2.50a i vbus mode 2.75a i vbus mode 3.00a i vbus mode (default) 2.5ma i vbus mode (usb suspend) l l l 65 460 550 650 745 800 950 1150 1425 1650 1900 2050 2350 2550 2800 80 480 570 670 770 850 1000 1230 1500 1750 2000 2175 2475 2725 2950 1.8 100 500 600 700 800 900 1025 1300 1575 1875 2125 2300 2600 2900 3100 2.5 ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma v float batsns regulated output voltage selected by i 2 c control. switching modes 3.45v setting (default) 3.55v setting 3.60v setting 3.80v setting l l l l 3.42 3.52 3.57 3.77 3.45 3.55 3.60 3.80 3.48 3.58 3.63 3.83 v v v v i charge regulated battery charge current selected by i 2 c control 12.50% charge current mode 18.75% charge current mode 25.00% charge current mode 31.25% charge current mode 37.50% charge current mode 43.75% charge current mode 50.00% charge current mode 56.25% charge current mode 62.50% charge current mode 68.75% charge current mode 75.00% charge current mode 81.25% charge current mode 87.50% charge current mode 93.75% charge current mode 100.0% charge current mode (default) 290 430 590 730 880 1025 1180 1330 1485 1635 1780 1915 2065 2210 2350 315 465 620 770 925 1075 1230 1385 1535 1685 1835 1980 2130 2280 2430 340 500 650 810 970 1125 1280 1440 1585 1735 1890 2045 2195 2350 2500 ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma i charge(max) regulated battery charge current 100.0% charge current mode, r prog = 340 3.44 3.57 3.70 a v out powerpath regulated output voltage (v bus power available) suspend mode, i vout = 1ma battery charger enabled, charging, batsns 3.19 v battery charger terminated or battery charger disabled 4.35 batsns 4.35 4.5 4.5 v v v v out(min) low battery instant-on output voltage (v bus power available) battery charger enabled, charging, batsns 3.0v 3.10 3.19 v www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 5 4156f electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a t j = 25c (note 2). v bus = 5v, batsns = 3.3v, dvcc = 3.3v, r clprog1 = r clprog2 = 1.21k, r prog = 499, unless otherwise noted. symbol parameter conditions min typ max units i vout v out current available before loading battery 2.5ma i vbus mode (usb suspend) 100ma i vbus mode, bat = 3.3v 500ma i vbus mode, bat = 3.3v 600ma i vbus mode, bat = 3.3v 700ma i vbus mode, bat = 3.3v 800ma i vbus mode, bat = 3.3v 900ma i vbus mode, bat = 3.3v 1.00a i vbus mode, bat = 3.3v 1.25a i vbus mode, bat = 3.3v 1.50a i vbus mode, bat = 3.3v 1.75a i vbus mode, bat = 3.3v 2.00a i vbus mode, bat = 3.3v 2.25a i vbus mode, bat = 3.3v 2.50a i vbus mode, bat = 3.3v 2.75a i vbus mode, bat = 3.3v 3.00a i vbus mode, bat = 3.3v 1 1.3 76 673 810 944 1093 1200 1397 1728 2072 2411 2700 2846 3154 3408 3657 ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma v prog prog pin servo voltage 12.50% charge current mode 18.75% charge current mode 25.00% charge current mode 31.25% charge current mode 37.50% charge current mode 43.75% charge current mode 50.00% charge current mode 56.25% charge current mode 62.50% charge current mode 68.75% charge current mode 75.00% charge current mode 81.25% charge current mode 87.50% charge current mode 93.75% charge current mode 100.0% charge current mode (default) 150 225 300 375 450 525 600 675 750 825 900 975 1050 1125 1200 mv mv mv mv mv mv mv mv mv mv mv mv mv mv mv v rechrg recharge battery threshold voltage threshold voltage relative to v float 96.6 97.6 98.4 % t terminate safety timer termination period selected by i 2 c control. timer starts when batsns v float 0.25-hour mode 0.5-hour mode 1-hour mode (default) 4-hour mode 0.23 0.47 0.95 3.81 0.27 0.53 1.06 4.24 0.30 0.59 1.17 4.66 hours hours hours hours v lowbat threshold voltage rising threshold hysteresis 2.65 2.8 130 2.95 v mv t badbat bad battery termination time batsns < (v lowbat C v lowbat ) 0.47 0.53 0.59 hours v c/x full capacity charge indication prog voltage selected by i 2 c control c/10 mode (i charge = 10%fs) (default) c/5 mode (i charge = 20%fs) c/20 mode (i charge = 5%fs) c/50 mode (i charge = 2%fs) 110 230 15 50 120 240 24 60 130 250 33 70 mv mv mv mv h prog ratio of i chgsns to prog pin current 1000 ma/ma h clprog1 (note 4) ratio of measured v bus current to clprog1 sense current clprog1 i vbus mode 990 ma/ma www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 6 4156f electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a t j = 25c (note 2). v bus = 5v, batsns = 3.3v, dvcc = 3.3v, r clprog1 = r clprog2 = 1.21k, r prog = 499, unless otherwise noted. symbol parameter conditions min typ max units h clprog2 (note 4) ratio of measured v bus current to clprog2 sense current 2.5ma i vbus mode (usb suspend) 100ma i vbus mode 500ma i vbus mode 600ma i vbus mode 700ma i vbus mode 800ma i vbus mode 900ma i vbus mode 1.00a i vbus mode 1.25a i vbus mode 1.50a i vbus mode 1.75a i vbus mode 2.00a i vbus mode 2.25 a i vbus mode 2.50a i vbus mode 2.75a i vbus mode 3.00a i vbus mode 19 79 466 557 657 758 839 990 1222 1494 1746 1999 2175 2477 2730 2956 ma/ma ma/ma ma/ma ma/ma ma/ma ma/ma ma/ma ma/ma ma/ma ma/ma ma/ma ma/ma ma/ma ma/ma ma/ma ma/ma v clprog1 clprog1 servo voltage in current limit clprog1 i vbus mode 1.2 v v clprog2 clprog2 servo voltage in current limit 2.5ma i vbus mode (usb suspend) 100ma C 3a i vbus modes 103 1.2 mv v f osc switching frequency 2.05 2.25 2.50 mhz r pmos high side switch on resistance 0.090 r nmos low side switch on resistance 0.080 r chg battery charger current sense resistance 0.040 i peak peak inductor current clamp 500ma C 3a i vbus modes 6.7 a step-up mode powerpath switching regulator (usb on-the-go) v bus output voltage 0ma i vbus 500ma 4.75 5.25 v v out input voltage 2.9 v i vbusotg output current limit 1.4 a i voutotgq v out quiescent current i vbus = 0ma 1.96 ma v clprog2 output current limit servo voltage 1.2 v v batsnsuvlo v batsns undervoltage lockout v batsns falling hysteresis 2.65 2.8 130 2.95 v mv t scfault short- circuit fault delay v bus < 4v 7.2 ms overvoltage protection, priority multiplexer and undervoltage lockout; usb input connected to usbsns through 3.6k resistor; wall input connected to wallsns through 3.6k resistor v uvlo usb input, wall input undervoltage lockout rising threshold falling threshold hysteresis 4.05 3.90 100 4.45 4.25 v v mv v duvlo usb input, wall input to batsns differential undervoltage lockout rising threshold falling threshold hysteresis 100 50 70 425 375 mv mv mv v ovlo usb input, wall input overvoltage protection threshold rising threshold 5.75 6.0 6.3 v v usbgtactv usbgt output voltage active usbsns < v usbovlo 2 ? v usbsns v v wallgtactv wallgt output voltage active wallsns < v wallovlo 2 ? v wallsns v www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 7 4156f electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a t j = 25c (note 2). v bus = 5v, batsns = 3.3v, dvcc = 3.3v, r clprog1 = r clprog2 = 1.21k, r prog = 499, unless otherwise noted. symbol parameter conditions min typ max units v usbgtprot usbgt output voltage protected usbsns > v usbovlo 0 v v wallgtprot wallgt output voltage protected wallsns > v wallovlo 0 v v usbgtload , v wallgtload usbgt, wallgt voltage under load 5v through 3.6k into wallsns, usbsns, i usbgt , i wallgt = 1a 8.4 8.9 v i usbsnsq usbsns quiescent current v usbsns = 5v, v usbsns > v wallsns v usbsns = 5v, v wallsns > v usbsns 27 54 a a i wallsnsq wallsns quiescent current v wallsns = 5v, v wallsns > v usbsns v wallsns = 5v, v usbsns > v wallsns 27 54 a a t rise ovgcap time to reach regulation c ovgcap = 1nf 1.2 ms irq pin characteristics i irq irq pin leakage current v irq = 5v 1 a v irq irq pin output low voltage i irq = 5ma 75 100 mv id pin characteristics i id id pin pull-up current v id = 0v 35 55 85 a v id_otg id pin threshold voltage id pin falling hysteresis 0.5 0.86 0.2 0.95 v v thermistor measurement system k offset v ntc / v ntcbias a /d lower range end v ntc / v ntcbias ratio below which only 0x00 is returned 0.113 v/v k high v ntc / v ntcbias a/d upper range end v ntc / v ntcbias ratio above which only 0x7f is returned 0.895 v/v k span a/d span coefficient (decimal format) 6.091 6.162 6.191 mv/v/ lsb d too_cold ntcval at ntc_too_cold (decimal format) warning threshold reset threshold 102 98 102 98 102 98 count count d hot_ fault ntcval at hot_ fault (decimal format) fault threshold reset threshold 19 23 19 23 19 23 count count i ntc ntc leakage current C100 100 na ideal diode v fwd forward voltage detection input power available, battery charger off 15 mv i 2 c port dvcc i 2 c logic reference level (note 3) 1.7 v max v i dvccq dvcc current scl/sda = 0khz 0.25 a v dvcc_uvlo dvcc uvlo 1.0 v address i 2 c address 0001 _001 [r/ w]b v ih , sda,scl input high threshold 70 % dvcc v il , sda,scl input low threshold 30 % dvcc i ih , sda,scl input leakage high sda, scl = dvcc C1 1 a i il , sda,scl input leakage low sda, scl = 0v C1 1 a v ol digital output low (sda) i sda = 3ma 0.4 v f scl clock operating frequency 400 khz t buf bus free time between stop and start condition 1.3 s www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 8 4156f electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a t j = 25c (note 2). v bus = 5v, batsns = 3.3v, dvcc = 3.3v, r clprog1 = r clprog2 = 1.21k, r prog = 499, unless otherwise noted. symbol parameter conditions min typ max units t hd_sda hold time after (repeated) start condition 0.6 s t su_sda repeated start condition set-up time 0.6 s t su_sto stop condition time 0.6 s t hd_ dat (out) data hold time 0 900 ns t hd_ dat (in) input data hold time 0 ns t su_ dat data set-up time 100 ns t low clock low period 1.3 s t high clock high period 0.6 s t f clock data fall time 20 300 ns t r clock data rise time 20 300 ns t sp spike suppression time 50 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC4156e is tested under pulsed load conditions such that t j t a . the LTC4156e is guaranteed to meet performance specifications from 0c to 85 c junction temperature. specifications over the C40c to 125 c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC4156i is guaranteed over the full C40c to 125 c operating junction temperature range. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ), where the package thermal impedance ja = 43c/w) note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3. v max is the maximum of v bus or batsns note 4. total input current is i vbusq + v clprog /r clprog ? (h clprog + 1). www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 9 4156f typical performance characteristics switching regulator efficiency battery charger total effciency vs battery voltage battery and v bus currents vs v out current battery and v bus currents vs v out current battery drain current vs temperature v out current (a) 0 current (a) 0.2 0.4 0.8 0.6 0.8 4155 g01 0 ?0.2 ?0.4 0.2 0.4 0.6 1.0 input current charge current 500ma input current limit mode v out current (a) 0 ?1.5 current (a) ?0.5 ?1.0 0 0.5 1.0 2.5 2.0 1.5 3.0 3.5 1 2 3 4 4155 g02 5 3a input current limit mode input current charge current current (a) 0 75 efficiency (%) power lost (w) 79 83 87 0.5 1.0 1.5 2.0 4156 g04 2.5 91 95 0 0.5 1.0 1.5 2.0 2.5 77 81 85 89 93 3.0 efficiency to v out efficiency to battery power lost to battery power lost to v out battery voltage (v) 2.4 0.50 load current (a) 0.75 1.00 1.25 1.50 1.75 2.7 3.0 3.3 3.6 4155 g06 3.9 500ma mode 900ma mode v float = 3.8v usb compliant load current available before discharging battery 500ma usb limited battery charge current vs battery voltage 100ma usb limited battery charge current vs battery voltage v out voltage vs battery voltage battery voltage (v) 2.4 charge current (a) 0.3 0.4 0.5 3.3 3.9 4156 g07 0.2 0.1 0 2.7 3.0 3.6 0.6 0.7 0.8 v float = 3.8v 12.5% charge current mode 100% charge current mode temperature (c) ?25 current (a) 6 8 10 95 4156 g03 4 2 5 7 9 3 1 0 5 35 65 ?10? 40 110 20 50 80 125 suspend mode (a) ship and store mode (a) v bus = 0v battery voltage (v) 2.4 85 90 95 3.6 4156 g05 80 75 2.7 3.0 3.3 3.9 70 65 60 efficiency (%) 12.5% charge current mode 100% charge current mode includes losses from 2 si7938dp ovp fets xfl4020-102me inductor and si5481du charger fet v float = 3.8v battery voltage (v) 2.4 charge current (ma) 30 40 50 3.3 3.9 4156 g08 20 10 0 2.7 3.0 3.6 60 70 80 v float = 3.8v battery voltage (v) 2.4 3.0 v out (v) 3.3 3.6 3.9 4.2 4.5 2.7 3.0 3.3 3.6 4155 g09 3.9 100% charge current mode 50% charge current mode 12.5% charge current mode charger disabled v float = 3.8v i vout = 0a t a = 25c (note 2). v bus = 5v, batsns = 3.3v, dvcc = 3.3v, r clprog1 = r clprog2 = 1.21k, r prog = 499, unless otherwise noted. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 10 4156f typical performance characteristics oscillator frequency vs temperature automatic charge current reduction vs battery voltage v bus current vs v bus voltage in usb suspend mode v out voltage vs v out current in usb suspend mode v bus current vs v out current in usb suspend mode battery charger resistance vs temperature normalized float voltage vs temperature t a = 25c (note 2). v bus = 5v, batsns = 3.3v, dvcc = 3.3v, r clprog1 = r clprog2 = 1.21k, r prog = 499, unless otherwise noted. temperature (c) ?40 charger total resistance (m) 50 55 60 60 4613 g10 45 40 35 ?15 10 35 85 resistance includes vishay siliconix si5481du external pmos battery voltage (v) 2.4 0 normalized charge current (%) 20 40 60 80 100 120 2.7 3.0 3.3 3.6 4155 g13 100% charge current mode 12.5% charge current mode v bus voltage (v) 2.5 0 v bus current (ma) 0.5 1.0 1.5 2.0 3.0 3.0 3.5 4.0 4.5 4155 g14 5.0 5.5 2.5 max not max v out current (ma) 0 v out voltage (v) 3.9 4.0 4.1 1.5 2.5 4155 g15 3.8 3.7 3.6 0.5 1.0 2.0 4.2 4.3 4.4 v out current (ma) 0 v bus current (ma) 1.5 2.0 2.0 4155 g16 1.0 0.5 0.5 1.0 1.5 2.5 2.5 static dvcc current vs dvcc voltage rising overvoltage lockout threshold vs temperature temperature (c) ?40 0.995 normalized float voltage (v) 0.996 0.998 0.999 1.000 ?10 20 35 125 4156 g11 0.997 ?25 5 50 65 95 110 80 500ma mode 100ma mode temperature (c) 2.17 oscillator frequency (mhz) 2.21 2.25 2.29 2.19 2.23 2.27 ?10 20 50 80 4156 g12 125110 ?25?40 5 35 65 95 dvcc voltage (v) 0 dvcc current (a) 0.3 0.4 0.5 3 5 4155 g17 0.2 0.1 0 1 2 4 0.6 0.7 0.8 temperature (c) 6.07 v bus voltage (v) 6.09 6.11 6.08 6.10 6.12 ?10 20 50 80 4156 g18 125110 ?25?40 5 35 65 95 www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 11 4156f typical performance characteristics t a = 25c (note 2). v bus = 5v, batsns = 3.3v, dvcc = 3.3v, r clprog1 = r clprog2 = 1.21k, r prog = 499, unless otherwise noted. ovp charge pump output vs input voltage undervoltage lockout thresholds vs temperature battery drain current vs battery voltage temperature (c) ?40 4.20 4.25 4.30 95 110 4155 g19 4.15 4.10 ?25 ?10 5 20 35 50 65 80 125 4.05 4.00 3.95 input uvlo threshold voltage (v) rising edge max falling edge max rising edge not max falling edge not max input voltage (v) 3.5 6 usbgt wallgt (v) 7 8 9 10 4.0 4.5 5.0 5.5 4155 g20 6.0 6.5 clprog voltage vs v bus current clprog voltage vs v out current v out voltage vs v out current v bus current (a) 0 0.8 1.0 1.4 1.5 2.5 4155 g23 0.6 0.4 0.5 1.0 2.0 3.0 3.5 0.2 0 1.2 clprog voltage (v) 3a input current limit mode v out current (a) 0 0.8 1.0 1.4 1.5 2.5 4155 g24 0.6 0.4 0.5 1.0 2.0 3.0 3.5 0.2 0 1.2 clprog voltage (v) 3a input current limit mode v out current (a) 0 v out voltage (v) 3.8 4.0 4 4155 g33 3.6 3.4 1 2 3 4.4 3a mode 4.2 500ma mode v batsns = 3.7v battery charger disabled 900ma mode battery voltage (v) 2.4 battery current (a) 2 3 3.6 4156 g22 1 0 2.7 3.0 3.3 3.9 4 ship-and-store mode, dvcc = 0v ship-and-store mode, dvcc = 3.3v dvcc = 0v dvcc = 3.3v www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 12 4156f pin functions sda (pin 1): data input/output for the i 2 c serial port. the i 2 c input levels are scaled with respect to dvcc for i 2 c compliance. dvcc (pin 2): logic supply for the i 2 c serial port. dvcc sets the reference level of the sda and scl pins for i 2 c compliance. it should be connected to the same power supply used to power the i 2 c pull-up resistors. irq (pin 3): open-drain interrupt output. the irq pin can be used to generate an interrupt due to a variety of maskable status change events within the LTC4156. id (pin 4): usb a-device detection pin. when wired to a mini- or micro-usb connector, the id pin detects when the a side of a mini or micro-usb cable is connected to the product. if the id pin is pulled down, and the lockout_id_pin bit is not set in the i 2 c port, the switch- ing powerpath operates in reverse providing usb power to the v bus pin from the battery . usb on-the-go power can only be delivered from the usb multiplexer path. clprog1 (pin 5): primary v bus current limit program- ming pin. a resistor from clprog1 to ground determines the upper limit of the current drawn from the v bus pin when clprog1 is selected. a precise measure of v bus current, h clprog1 C1 , is sent to the clprog1 pin. the switching regulator increases power delivery until clprog 1 reaches 1.2v. therefore, the current drawn from v bus will be limited to an amount given by the 1.2v reference voltage, h clprog1 and r clprog1 . typically clprog1 is used to override the usb compliant input current control pin, clprog2, in applications where usb compliance is not a requirement. this would be use- ful for applications that use a dedicated wall adapter and would rather not be limited to the 500mw start-up value required by usb specifications. if usb compliance is a requirement at start-up, clprog1 should be connected to clprog2 and a single resistor should be used. see the clprog2 pin description. in usb noncompliant designs, the user is encouraged to use an r clprog1 value that best suits their application for start-up current limit. see the operation section for more details. clprog2 (pin 6): secondary v bus current limit pro- gram pin. clprog2 controls the v bus current limit when either selected via i 2 c command or when clprog1 and clprog2 are shorted together. when selected, a resistor from clprog2 to ground determines the upper limit of the current drawn from the v bus pin. like clprog1, a precise fraction of v bus current, h clprog2 C1 , is sent to the clprog2 pin. the switching regulator increases power delivery until clprog2 reaches 1.2v. therefore, the cur - rent drawn from v bus will be limited to an amount given by the 1.2v reference voltage, h clprog2 and r clprog2 . there are a multitude of ratios for h clprog 2 available by i 2 c control, three of which correspond to the 100ma, 500ma and 900ma usb specifications. clprog2 is also used to regulate maximum input current in the usb suspend mode and maximum output current in usb on-the-go mode. if clprog 1 and clprog 2 are shorted together at the onset of available input power, the LTC4156 selects clprog2 in the 100ma usb mode to limit input current. this ensures usb compliance if so desired. for usb compliance in all modes, the user is encouraged to make r clprog2 equal to the value declared in the electrical characteristics. wallsns ( pin 7): highest priority multiplexer input and overvoltage protection sense input . wallsns should be connected through a 3.6k resistor to a high priority input power connector and one drain of two source -connected n-channel mosfet pass transistors. when voltage is detected on wallsns , it draws a small amount of current to power a charge pump which then provides gate drive to wallgt to energize the external transistors. if the input voltage exceeds v ovlo , wallgt will be pulled to gnd to disable the pass transistors and protect the LTC4156 from high voltage. usbsns (pin 8): lowest priority multiplexer input and overvoltage protection sense input. usbsns should be connected through a 3.6k resistor to a low priority input power connector and one drain of two source -connected n-channel mosfet pass transistors. when voltage is detected on usbsns, and no voltage is detected on wallsns , usbsns draws a small amount of current to power a charge pump which then provides gate drive to www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 13 4156f pin functions usbgt to energize the external transistors. if the input voltage exceeds v ovlo , usbgt will be pulled to gnd to disable the pass transistors and protect the LTC4156 from high voltage. power detected on wallsns is prioritized over usbsns. if power is detected on both wallsns and usbsns, by default, only wallgt will receive drive for its pass tran- sistors. see the operations section for further information about programmable priority. usbgt (pin 9): overvoltage protection and priority mul- tiplexer gate output. connect usbgt to the gate pins of two source -connected external n-channel mosfet pass transistors. one drain of the transistors should be con- nected to v bus and the other drain should be connected to a low priority dc input connector. in the absence of an overvoltage condition, this pin is driven from an internal charge pump capable of creating sufficient overdrive to fully enhance the pass transistors. if an overvoltage condition is detected, usbgt is brought rapidly to gnd to prevent damage to the ltc 4156 . usbgt works in conjunction with usbsns to provide this protection. usbgt also works in conjunction with wallsns to determine power source prioritization. see the operation section. ovgcap ( pin 10): overvoltage protection capacitor output. a 0.1f capacitor should be connected from ovgcap to gnd. ovgcap is used to store charge so that it can be rapidly moved to wallgt or usbgt. this feature provides faster power switchover when multiple inputs are supported by the end product. wallgt (pin 9): overvoltage protection and priority mul- tiplexer gate output. connect wallgt to the gate pins of two source -connected external n-channel mosfet pass transistors. one drain of the transistors should be con- nected to v bus and the other drain should be connected to a high priority input connector. in the absence of an overvoltage condition, this pin is driven from an internal charge pump capable of creating sufficient gate drive to fully enhance the pass transistors. if an overvoltage condition is detected, wallgt is brought rapidly to gnd to prevent damage to the LTC4156. wallgt works in conjunction with wallsns to provide this protection. wallgt also works in conjunction with usbsns to determine power source prioritization. see the operation section. v c (pin 12): compensation pin. a 0.047f ceramic ca- pacitor on this pin compensates the switching regulator control loops. v outsns ( pin 13): output voltage sense input . connecting v outsns directly to the v out bypass capacitor ensures that v out regulates at the correct level. ntcbias (pin 14): ntc thermistor bias output . connect a bias resistor between ntcbias and ntc, and a thermistor between ntc and gnd . the value of the bias resistor should usually be equal to the nominal value of the thermistor. ntc ( pin 15): input to the negative temperature coefficient thermistor monitoring circuit . the ntc pin connects to a negative temperature coefficient thermistor, which is typically copackaged with the battery , to determine if the battery is too cold to charge or if the battery is dangerously hot. if the battery s temperature is out of range, charging is paused until the battery temperature re-enters the valid range. a low drift bias resistor is required from ntcbias to ntc and a thermistor is required from ntc to ground. the thermistors temperature reading is continually digitized by an analog-to-digital converter and may be read back at any time via the i 2 c port. batsns (pin 16): battery voltage sense input. for proper operation, this pin must always be connected to the bat- tery . for fastest charging, connect batsns physically close to the lithium iron phosphate cells positive terminal. depending upon available power and load, a lifepo 4 bat- tery connected to the batsns pin will either be charged from v out or will deliver system power to v out via the required external p-channel mosfet transistor. batgate (pin 17): battery charger and ideal diode ampli- fier control output . this pin controls the gate of an external p-channel mosfet transistor used to charge the lifepo 4 cell and to provide power to v out when the system load exceeds available input power. the source of the p - channel mosfet should be connected to chgsns and the drain should be connected to batsns and the battery. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 14 4156f pin functions prog ( pin 18): charge current program and monitor pin. a resistor from prog to gnd programs the maximum battery charge rate. the LTC4156 features i 2 c programmability enabling software selection of fifteen charge currents that are inversely proportional to a single user-supplied programming resistor. chgsns (pins 19, 20): battery charger current sense pin. an internal current sense resistor between v out and chgsns monitors battery charge current. chgsns should be connected to the source of an external p - channel mosfet transistor. v out (pins 21, 22): output voltage of the switching powerpath controller and input voltage of the battery charging system. the majority of the portable product should be powered from v out . the LTC4156 will partition the available power between the external load on v out and the battery charger. priority is given to the external load and any extra power is used to charge the battery . an ideal diode control function from batsns to v out ensures that v out is powered even if the load exceeds the allotted power from v bus or if the v bus power source is removed. v out should be bypassed with a low impedance multilayer ceramic capacitor of at least 22f. v bus (pins 23, 24, 25): input voltage for the powerpath step-down switching regulator and output voltage for the usb on-the-go step-up switching regulator. v bus may be connected to the usb port of a computer or a dc output wall adapter or to one or both optional overvolt - age protection/multiplexer compound transistors. v bus should be bypassed with a low impedance multilayer ceramic capacitor. sw (pins 26, 27): switching regulator power transmis - sion pin. the sw pin delivers power from v bus to v out via the step-down switching regulator and from v out to v bus via the step-up switching regulator. a 1h inductor should be connected from sw to v out . see the applica- tions information section for a discussion of current rating . scl (pin 28): clock input for the i 2 c serial port. the i 2 c input levels are scaled with respect to dvcc for i 2 c compliance. gnd (exposed pad pin 29): the exposed pad must be soldered to the pcb to provide a low electrical and ther - mal impedance connection to the printed circuit boards ground. a continuous ground plane on the second layer of a multilayer printed circuit board is strongly recommended . www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 15 4156f block diagram + ? + ? + ? 1.200v ntc clprog1 clprog2 prog ntcbias 7 t usbgt usbsns 2 4156 bd single-cell lifepo 4 25m external pmos ex: vishay- siliconix si548idu average usb input and otg output current limit controller input undervoltage current limit contoller ideal diode enable charger greater of batsns or 3.19v to system load automatic charge current reduction controller ov uv + ? 0.9v + ? i 2 c programmable mask i 2 c + to wall adaptor to usb + ? + ? enable usb otg uv ov v bus v bus v bus wallsns wallgt ovgcap id chgsns chgsns batgate 3.19v batsns v out v outsns v out dvcc scl v out sda irq + ? usb otg short detector + ? usb on-the-go boost control pwm and gate drive v c 4.30v + ? + ? v out controller 4.35v + ? v float controller + ? charge current controller end-of-charge indication sw sw dv cc n ntc a/d i 2 c 2 v float d/a 3.45v to 3.8v i 2 c 2 c/x d/a 24mv to 240mv i 2 c 4 i charge d/a 0.15v to 1.2v www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 16 4156f timing diagrams ack 1 2 3 write address r/ w 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 ack stop start sda scl ack sub address input data byte optional 4155 td01 i 2 c write protocol i 2 c read protocol timing diagram ack 1 2 3 read address r/ w 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 a7 a6 a5 a4 a3 a2 a1 a0 start sda scl nack output data byte 4155 td02 t su, dat t hd, sta t hd, dat sda scl t su, sta t hd, sta t su, sto 4155 td03 t buf t low t high start condition (s) repeated start condition (s r ) stop condition (p) start condition (s) t r t f t sp www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 17 4156f table 2. i 2 c map register access sub address d7 d6 d5 d4 d3 d2 d1 d0 reg0 write/ readback 0x00 disable input uvcl 0 reserved lockout usb otg id pin usb current limit reg1 write/ readback 0x01 input priority safety timer wall current limit reg2 write/ readback 0x02 charge current float voltage c/x detection reg3 read 0x03 charger status id pin detection status boost enable status thermistor status low battery status reg4 read 0x04 external power good usbsns good wallsns good input current limit active input uvcl active ovp active otg fault bad cell fault reg5 read 0x05 thermistor value thermis- tor warning reg6 write/ readback clear interrupt * disarm ship-and- store mode* 0x06 enable charger interrupts enable fault interrupts enable external power interrupts enable usb otg interrupts enable input current limit interrupts enable input uvcl interrupts enable usb on-the-go 0 reserved reg7 write arm ship- and-store mode** 0 x07 0 required 0 required 0 required 0 required 0 required 0 required 0 required 0 required *interrupts are cleared and ship-and-store mode is disarmed during the acknowledge clock cycle following a full data byte written to sub address 0x06. reading data from sub address 0x06 has no effect. **ship-and-store mode is armed during the acknowledge clock cycle following a full data byte written to sub address 0x07. the data written to sub address 0x07 is ignored. reading from sub address 0x07 has no effect and the returned data is undefined, independent of the arming state of ship-and-store mode. operation i 2 c www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 18 4156f operation introduction the ltc 4156 is an advanced i 2 c controlled power manager and lifepo 4 battery charger designed to efficiently transfer up to 15w from a variety of sources while minimizing power dissipation and easing thermal budgeting constraints. by decoupling v out and the battery , the innovative instant- on powerpath architecture ensures that the application is powered immediately after external voltage is applied, even with a completely dead battery , by prioritizing power to the application. since v out and the battery are decoupled, the LTC4156 includes an ideal diode controller. the ideal diode from the battery to v out guarantees that ample power is always available to v out even if there is insufficient or absent power at v bus . the LTC4156 includes a monolithic step-down switch- ing battery charger for usb support, wall adapters and other 5v sources . by incorporating a unique input current measurement and control system, the switching charger interfaces seamlessly to wall adapters and usb ports without requiring application software to monitor and adjust system loads. because power is conserved , the LTC4156 allows the load current on v out to exceed the current drawn by the usb port or wall adapter, making maximum use of the allowable power for battery charging without exceeding the usb or wall adapter power delivery specifications. a wide range of input current settings as well as battery charge current settings are available for selection by i 2 c. using only one inductor, the switching powerpath can operate in reverse, boosting the battery voltage to provide 5v power at its input pin for usb on-the-go applications. in the usb-otg mode, the switching regulator supports usb high power loads up to 500ma. protection circuits ensure that the current is limited and ultimately the channel is shut down if a fault is detected on the usb connector. to support usb low power mode, the LTC4156 can deliver power to the external load and charge the battery through a linear regulator while limiting input current to less than 100 ma. the LTC4156 also features a combination overvoltage protection circuit / priority multiplexer which prevents damage to its input caused by accidental application of high voltage and selects one of two high power input connectors based on priority. a thermistor measurement subsystem periodically monitors and reports the battery s thermistor value via the onboard i 2 c port. the same circuit then reports when dangerous battery temperatures are reached and can autonomously pause charging. to minimize battery drain when a device is connected to a suspended usb port, an ldo from v bus to v out provides the allowable usb suspend current to the application. an interrupt subsystem can be enabled to alert the host microprocessor of various status change events so that system parameters can be varied as needed by system software. several status change event categories are maskable for maximum flexibility. to eliminate battery drain between manufacture and sale, a ship-and-store feature reduces the already low battery standby current to nearly zero and optionally disconnects power from downstream circuitry. an input undervoltage amplifier optionally prevents the input voltage from decreasing below 4.3v when a resistive cable or current limited supply is providing input power to the LTC4156. finally, the LTC4156 has considerable adjustability built in so that power levels and status information can be controlled and monitored via the simple 2-wire i 2 c port. input current-limited step-down switching charger power delivery from v bus to v out is controlled by a 2.25mhz constant-frequency step-down switching regu- lator. the switching regulator reduces output power in response to one of six regulation loops, including battery voltage, battery charge current, output voltage, input cur - rent, input undervoltage , and external pmos charger fet power dissipation. for usb low power (100ma) and usb suspend (2.5ma) modes, the switching regulator is dis- abled and power is transmitted through a linear regulator. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 19 4156f battery float voltage regulation when the battery charger is enabled, the switching regula- tor will reduce its output power to prevent v batsns from exceeding the programmed battery float voltage, v float . the float voltage may be selected from among four pos- sible choices via the i 2 c interface using bits vfloat [1:0]. refer to table 11. battery charge current regulation and low cell trickle charge the switching regulator will also reduce its output power to limit battery charge current, i charge , to a programmed maximum value . the battery charge current is programmed using both a resistor, r prog , between prog and ground to set default maximum charge current plus i 2 c adjust- ability to optionally reduce programmed charge current. the battery charge current loop mirrors a precise fraction of the battery charge current, i bat , to the prog pin , then reduces switching regulator output power to limit the resultant voltage, v prog , to one of fifteen possible servo reference voltages. the following expression may be used to determine the battery charge current at any time by sampling the prog pin voltage. i bat = v prog r prog ? 1000 this expression may also be used to calculate the required value of r prog for any desired charge current. the resis- tor value required to program default maximum charge current may be found by substituting v prog = 1.200 and solving for r prog . the other fourteen settings are i 2 c selectable using icharge[3:0] and reduce the charge current in 6.25% steps. the resulting limits may be found by substituting r prog and the relevant v prog servo volt- age from table?10. the maximum charge current should be set based on the cell size and maximum charge rate without regard to input current setting or input power source. the LTC4156 monitors the voltage across the external pmos transistor and automatically reduces the cur - rent regulation servo voltage at v prog to limit power dissipation in the transistor. during normal operation, the pmos channel is fully enhanced and power dissipation is typically under 100mw. starting when the battery voltage is below approximately 2.94v, the charge current servo voltage will be gradually reduced from its i 2 c programmed value to a minimum value between 75 mv and 100 mv when the battery is below v lowbat , typically 2.8v. this charge current reduction has the combined effect of protecting the external pmos transistor from damage due to excessive heat, while also trickle charging the excessively depleted cell to maximize battery health and lifetime. peak power dissipation in the external pmos transistor is limited to approximately 700mw. figure 1 shows the relation- ship between battery voltage, charge current and power dissipation. operation figure 1. v out minimum voltage regulation v out voltage regulation a third control loop reduces power delivery by the switch- ing regulator in response to the voltage at v out , which has a nonprogrammable servo voltage of 4.35v. when the battery charger is enabled, v out is connected to batsns through the internal charge current sense resistor and the external pmos battery fet. the two node voltages will differ only by the i t r drop through the two devices, effectively keeping v out below its servo point for the duration of the charge cycle. the LTC4156 will attempt to prevent v out from falling below approximately 3.19v when the battery is deeply battery voltage (v) 2.3 charge current (a) pfet dissipation (w) 1.5 2.0 2.5 2.9 3.3 3.9 4156 f01 1.0 0.5 0 0.5 0.7 0.8 0.3 0.4 0.6 0.2 0.1 0 2.5 2.7 3.1 3.5 3.7 i charge 100% mode (2.4a) i charge 50% mode (1.2a) p diss 100% mode (2.4a) p diss 50% mode (1.2a) v float = 3.8v www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 20 4156f discharged . this feature allows instant - on operation when the low state of charge would otherwise prevent operation of the system. if the system load plus battery charger load exceeds the available input power, battery charge current will be sacrificed to prioritize the system load and maintain the switching regulator output voltage while continuing to observe the input current limit. if the system load alone exceeds the power available from the input, the output voltage must fall to deliver the additional current, with supplemental current eventually being sup- plied by the battery. input current regulation to meet the maximum load specification of the available supply ( usb / wall adapter ), the switching regulator contains a measurement and control system which ensures that the average input current is below the level programmed at the clprog1 or clprog2 pin and the i 2 c port. con- necting a single 1% tolerance resistor of the recommended value to both the clprog 1 and clprog 2 pins guarantees compliance with the 2.5ma , 100ma , 500ma, and 900ma usb 2.0/3.0 current specifications, while also permitting other i 2 c selectable current limits up to 3a. the input current limit is independently selectable for each of the two inputs, with the usbilim[4:0] and wallilim [4:0] bits in the i 2 c port. the usb input current limit setting resets to 100ma when power is removed from its respec- tive input. the wall input current limit setting resets to 100ma when power is removed from both the usb and wall inputs . refer to alternate default input current limit in the operation section to program a non usb compli- ant default input current limit for use with wall adapters or other power sources . refer to table 7 for a complete listing of i 2 c programmable input current limit settings. if the combined external load plus battery charge current is large enough to cause the switching power supply to reach the programmed input current limit, the battery charger will reduce its charge current by precisely the amount necessary to enable the external load to be satisfied. even if the battery charge current is programmed to exceed the allowable input power, the specification for average input current will not be violated; the battery charger will reduce its current as needed. furthermore, if the load at v out exceeds the programmed power level from v bus , the extra load current will be drawn from the battery via the ideal diode independent of whether the battery charger is enabled or disabled. input undervoltage current limit the LTC4156 can tolerate a resistive connection to the input power source by automatically reducing power transmission as the v bus pin drops to 4.3v preventing a possible uvlo oscillation. the undervoltage current limit feature can be disabled by i 2 c using the disable_input_ uvcl bit. refer to table 5. usb on-the-go 5v boost converter the LTC4156 switching regulator can be operated in reverse to deliver power from the battery to v bus while boosting the v bus voltage to 5v. this mode can be used to implement features such as usb on-the-go without any additional magnetics or other external components. the step-up switching regulator may be enabled in one of two ways. the LTC4156 can optionally monitor the id pin of a usb cable and autonomously start the step-up regulator when a host- side a / b connector is detected with a grounded id pin. the switching regulator may also be enabled directly with the request_otg i 2 c command. note that the step - up regulator will not operate if input power is present on either the usb or wall input, or if the battery voltage is below v lowbat , typically 2.8v . the i 2 c status bits otg_enabled, lowbat and otg_ fault can be used to determine if the step-up converter is running. refer to id pin detection in the operation section for more information about the autonomous step-up regulator start-up. the step - up regulator only provides power to the usb input . it is not possible to provide power to the wall input . the i 2 c priority setting has no effect on step-up regulator operation. refer to dual input overvoltage protection and undervoltage lockout in the operation section for more information about multiple input operation. the switching regulator is guaranteed to deliver 500ma to v bus and will limit its output current to approximately 1.4a while allowing v bus to fall when overloaded. if a short-circuit fault is detected, the channel will be shut down after approximately 8ms and the problem will be reported with the i 2 c status bit otg_ fault. operation www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 21 4156f id pin detection for usb on-the-go compatibility, the step-up switching regulator can optionally start autonomously when the grounded id pin in the a side of an on-the-go cable is detected. the id pin is monitored at all times. its status is reported in the i 2 c bit id_detect, reporting true when the id pin is grounded. optionally, any change in id_pin _detect may trigger an interrupt request to notify the system processor. unless the i 2 c lockout_ id_ pin bit has been set, id pin detection will also automatically start the step-up regulator. note that lockout_id_pin locks out automatic start-up, but not monitoring of the id pin. also, the request_otg command may be used to enable the step- up regulator, independent of the state of id_ pin_ detect and lockout_id_pin. note that the regulator will not start if input power is already present on either input. the i 2 c status bits otg_ enabled and otg_ fault can be used to determine if the regulator is running. the id pin detection circuit will report a short on the id pin for id pin impedances lower than approximately 24k. the usb battery charging specification rev 1.1 added additional signaling to the id pin, specifying other possible id pin resistances of rid_a, rid_b and rid_c. these impedances are all larger than the 24k threshold and will typically not cause an id pin short detection. dual input overvoltage protection and undervoltage lockout the LTC4156 can provide overvoltage protection to its two power inputs with minimal external components, as shown in figure 2. the LTC4156 acts as a shunt regulator when the input is overvoltage , clamping usbsns or wallsns to 6 v . resis - tors r1 and r2 should be 3.6k and be rated appropriately for the worst - case power dissipation during an overvoltage event. the power dissipated in the resistor is given by the following expression: p resistor = (v overvoltage ? 6v) 3.6k 2 for example, a typical 0201 size resistor would be ap- propriate for possible overvoltage events up to 19v. an 0402 size resistor would be appropriate up to 20v, an 0603 up to 24v, an 0805 up to 27v, and a 1206 up to 35v. additional power derating may be necessary at elevated ambient temperature. the maximum allowed shunt cur - rent into the usbsns and wallsns pins constrains the upper limit of protection to 77v. the drain- source voltage rating, v ds , of n-channel fets mn1-mn2 must be appropriate for the level of overvolt - age protection desired, as the full magnitude of the input voltage is applied across one of these devices. the drain- source voltage rating of n-channel fets mn3- mn4 need only be as high as the protection threshold, typically 6.0v. mn3-mn4 are not required for overvoltage protection , but are required to block current from circulating from one input to the other through the unused channels fet body diode . for single - input applications , only a single power fet is required. refer to alternate input power configurations in the applications information section for implementation details. negative voltage protection can be added by reconfiguring the circuit without adding any additional power transistors . refer to alternate input power configurations in the ap- plications information section for implementation details. for an input (usb or wall ) to be considered a valid power source , it must satisfy three conditions. first, it must be above a minimum voltage, v uvlo . second, it must be greater than the battery voltage by a minimum of v duvlo . lastly , it must be below the overvoltage protection threshold voltage , v ovlo . the usbsns and wallsns pins each draw a small current which causes a voltage offset between the usb and wall inputs and the usbsns and figure 2. dual-input overvoltage protection multiplexer v bus to usb input to wall input ovgcap usbgt usbsns wallgt LTC4156 wallsns 4156 f02 mn1 r1 r2 mn3 mn2 mn4 operation www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 22 4156f wallsns pins. the voltage threshold values previously listed and specified in the electrical characteristics table are valid when each input is connected to its respective sense pin through a 3.6k resistor. the status of the usb and wall inputs is monitored continuously and reported by i 2 c, with the option of generating several interrupts. when all three conditions previously listed are true, the LTC4156 will report the input valid by asserting usbsnsgd or wallsnsgd in the i 2 c port. optionally, if external power interrupts are enabled, an interrupt request will be generated. when power is applied simultaneously to both inputs, the LTC4156 will draw power from the wall input by default. if the i 2 c priority bit is asserted, the LTC4156 will instead draw power from the usb input when both inputs are present. the usb on-the-go step-up regulator delivers power only to the usb input, and the prior- ity bit is ignored in this mode. the input current limits usbilim[4:0] and wallilim [4:0] also reset to 100ma default mode under different criteria. in all other respects, the two inputs are identical. an optional capacitor may be placed between the ovgcap pin and gnd to minimize input current disruption when switching from one input to the other while operating at high power levels . the capacitor must be rated to withstand at least 13v and should be approximately ten times larger than the total gate capacitance of the series nmos power transistors. capacitance on this pin can also be used to slow the gate charging if the application requires controlled inrush current to any additional input capacitance on the v bus pin. if fast switching between input or inrush control is not necessary, ovgcap may be left unconnected. if overvoltage protection is not necessary in the application , connect usbsns to v bus with a 3.6k resistor, as shown in figure 3. if the usb on-the-go step-up regulator is not used in the application, it is also possible to connect wallsns to v bus through 3.6k and leave usbsns open. 100ma linear battery charger mode the LTC4156 features a mode to support usb low power operation. total input current to the LTC4156 is guaranteed to remain below 100ma in this mode when the recom- mended resistor is used on the clprog2 pin. the step- down switching regulator does not operate in this mode. instead, a linear regulator provides power from v bus to v out and the battery . the linear battery charger follows the same constant-current/constant-voltage algorithm as the switching regulator, but regulates input current rather than battery charge current. the voltage on the clprog2 pin represents the input current in this mode, using the expression: i vbus = v clprog2 r clprog2 ? 80 ( ) battery charge current is represented by the voltage on the prog pin, but it is not regulated in this mode. i charge = v prog r prog ? 1000 ( ) v out will generally be very close to the battery voltage when the battery charger is enabled, except when the battery voltage is very low, the LTC4156 will increase the imped- ance between v out and batsns to facilitate instant-on operation. if the system load plus battery charge current exceeds the available input current, battery charge current will be sacrificed to give priority to the load. if the system load alone exceeds the available input current, v out must fall to the battery voltage so that the battery may provide the supplemental current. the battery will charge to the float voltage specified by the i 2 c setting vfloat[1:0]. see table 11. when the battery charger is disabled or terminated, v out will be regulated to 4.35v. operation v bus to power input ovgcap usbgt usbsns wallgt LTC4156 wallsns 4156 f03 r1 figure 3. no overvoltage protection www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 23 4156f 2.5ma linear suspend mode the LTC4156 can supply a small amount of current from v bus to v out to power the system and reduce battery discharge when the product has access to a suspended usb port. when the system load current is less than the current available from the suspended usb port, the volt- age at v out will be regulated to 4.35v. if the system load current exceeds usb input current limit, the voltage at v out will fall to the battery voltage and any supplemental current above that available from the usb port will be supplied by the battery . clprog2 will servo to 103mv in current limit. battery charging is disabled in suspend mode . either the usb or wall input may utilize this current limited suspend mode by programming the appropriate setting in the respective usbilim or wallilim register. ideal diode and minimum v out controller the LTC4156 features an ideal diode controller to ensure that the system is provided with sufficient power even when input power is absent or insufficient. this requires an external pmos transistor with its source connected to chgsns, gate to batgate , and drain to batsns . the controller modulates the gate voltage of the pmos tran - sistor to allow current to flow from the battery to v out to power the system while blocking current in the opposite direction to prevent overcharging of the battery. the ideal diode controller has several modes of operation. when input power is available and the battery is charging, the pmos gate will generally be grounded to maximize conduction between the switching regulator and the battery for maximum efficiency. if the battery is deeply discharged, the LTC4156 will automatically increase the impedance between the switching regulator and the battery enough to prevent v out from falling below approximately 3.19v. power to the system load is always prioritized over battery charge current. increasing the impedance between v out and the battery does not necessarily affect the battery charge current, but it may do so for one of the following two reasons: 1. the charge current will be limited to prevent excessive power dissipation in the external pmos as it becomes more resistive. charge current reduction begins when the voltage across the pmos reaches approximately 250mv, and can reduce the charge current as low as 8% full scale. maximum power dissipation in the pmos is limited to approximately 700mw with r prog = 499. 2. when limited power is available to the switching regula - tor because either the programmed input current limit or input undervoltage current limit is active, charge current will automatically be reduced to prioritize power delivery to the system at v out . v out will be main- tained at 3.19v as long as possible without exceeding the input power limitation. if the system load alone requires more power than is available from the input after charge current has been reduced to zero, v out must fall to the battery voltage as the battery begins providing supplemental power. when input power is available, but the battery charger is disabled or charging has terminated, v out and the bat- tery are normally disconnected to prevent overcharging the battery . if the power required by the system should exceed the power available from the input, either because of input current limit or input undervoltage current limit, v out will fall to the battery voltage and any additional cur - rent required by the load will be supplied by the battery through the ideal diode. when input power is unavailable, the ideal diode switches to a low power mode which maximizes conduction and power transmission efficiency between v out and the bat- tery by grounding the pmos gate. finally, when ship-and-store mode is activated, the ideal diode is shut down and batgate is driven to the battery voltage to prevent conduction through the pmos. note that with a single fet, conduction to v out is still possible through the body connection diode. refer to low power ship-and-store mode in the operation section for more information about this mode. operation www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 24 4156f figure 4. ship-and-store mode required components to enforce downstream (v out ) shutdown chgsns batsns batgate LTC4156 4156 f04 + low power ship-and-store mode the LTC4156 can reduce its already low standby current to approximately 1a in a special mode designed for shipment and storage. unlike normal standby mode, in this mode the external pmos gate is driven to the battery voltage to disable fet conduction through the external pmos. this mode may be used to cut off all power to any downstream load on v out to maximize battery life between product manufacture and sale. note that the bulk connection inside the external pmos will provide a con- ductive path from the battery to v out , independent of the voltage on its gate. to block conduction to v out , typically two pmos transistors must be connected in series with either the sources or drains of each device connected in the center, as shown in figure 4. if the application does not require the battery to be isolated from downstream devices, significant power savings in the LTC4156 may still be realized by activating this mode. ship-and-store mode is armed following the acknowledge of any data byte written to sub address 0x07 by the i 2 c bus master. the contents of the data byte are ignored, but the full byte and acknowledge clock cycle must be sent. ship-and-store mode is activated as v bus falls below ap- proximately 1 v , or immediately if no input power is present when the i 2 c command is issued. v bus quiescent current falls to nearly zero when power is removed from the usb and wall inputs , resulting in a delay of up to several hours for v bus to self-discharge to the 1v activation threshold. faster activation may be achieved by connecting a 1m resistor between v bus and gnd. reading from sub ad- dress 0x07 has no effect on arming or activation and the returned data is undefined, independent of the arming or activation state. once engaged, ship-and-store mode can be disengaged by applying power to the usb or wall input or by writ- ing any full data byte and acknowledge clock cycle to sub address 0x06 if the i 2 c bus master is still powered. i 2 c interface the LTC4156 may communicate with a bus master using the standard i 2 c 2-wire interface . the timing diagram shows the relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources , such as the ltc1694 smbus accelerator, are required on these lines. the LTC4156 is both a slave receiver and slave transmitter. the i 2 c control signals, sda and scl, are scaled internally to the dvcc supply. dvcc should be connected to the same power supply as the bus pull-up resistors. the i 2 c port has an undervoltage lockout on the dvcc pin. when dvcc is below approximately 1v, the i 2 c serial port is cleared, the LTC4156 is set to its default configuration, pending interrupts will be cleared, and future interrupts will be disabled. bus speed the i 2 c port is designed to operate at speeds of up to 400khz. it has built-in timing delays to ensure correct operation when addressed from an i 2 c compliant master device. it also contains input filters designed to suppress glitches. start and stop conditions a bus master signals the beginning of communications by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. the master may transmit either the slave write or the slave read address. once data is written to the ltc 4156, the master may transmit a stop condi- tion which commands the LTC4156 to act upon its new command set. a stop condition is sent by the master by transitioning sda from low to high while scl is high. operation www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 25 4156f byte format each frame sent to or received from the LTC4156 must be eight bits long, followed by an extra clock cycle for the acknowledge bit. the data should be sent to the LTC4156 most significant bit (msb) first. master and slave transmitters and receivers devices connected to an i 2 c bus may be classified as either master or slave. a typical bus is composed of one or more master devices and a number of slave devices. some devices are capable of acting as either a master or a slave, but they may not change roles while a transaction is in progress. the transmitter/receiver relationship is distinct from that of master and slave. the transmitter is responsible for control of the sda line during the eight bit data portion of each frame. the receiver is responsible for control of sda during the ninth and final acknowledge clock cycle of each frame. all transactions are initiated by the master with a start or repeat start condition. the master controls the active (falling) edge of each clock pulse on scl, regardless of its status as transmitter or receiver. the slave device never brings scl low, but may extend the scl low time to implement clock stretching if necessary . the LTC4156 does not clock stretch and will never hold scl low under any circumstance. the master device begins each i 2 c transaction as the transmitter and the slave device begins each transaction as the receiver. for bus write operations, the master acts as the transmitter and the slave acts as receiver for the duration of the transaction. for bus read operations, the master and slave exchange transmit / receive roles following the address frame for the remainder of the transaction. acknowledge the acknowledge signal (ack) is used for handshaking between the transmitter and receiver. when the LTC4156 is written to, it acknowledges its write address as well as the subsequent data bytes as a slave receiver. when it is read from, the LTC4156 acknowledges its read address as a slave receiver. the LTC4156 then changes to a slave transmitter and the master receiver may optionally acknowl - edge receipt of the following data byte from the LTC4156. the acknowledge related clock pulse is always generated by the bus master. the transmitter (master or slave) releases the sda line (high) during the acknowledge clock cycle. the receiver (slave or master) pulls down the sda line during the acknowledge clock pulse so that it is a stable low during the high period of this clock pulse. when the LTC4156 is read from, it releases the sda line after the eighth data bit so that the master may acknowl- edge receipt of the data. the i 2 c specification calls for a not acknowledge (nack) by the master receiver following the last data byte during a read transaction. upon receipt of the nack, the slave transmitter is instructed to release control of the bus. because the LTC4156 only transmits one byte of data under any circumstance , a master ac- knowledging or not acknowledging the data sent by the LTC4156 has no consequence. the LTC4156 will release the bus in either case. slave address the LTC4156 responds to a 7-bit address which has been factory programmed to 0b0001_001[r/w]. the lsb of the address byte, known as the read/write bit, should be 0 when writing data to the LTC4156, and 1 when reading data from it. considering the address an 8-bit word, then the write address is 0x12, and the read address is 0x13. the LTC4156 will acknowledge both its read and write addresses. sub addressed access the LTC4156 has four command registers for control input and three status registers for status reporting. they are accessed by the i 2 c port via a sub addressed pointer system where each sub address value points to one of the seven control or status registers within the LTC4156. the sub address pointer is always the first byte written immediately following the LTC4156 write address dur - ing bus write operations. the sub address pointer value persists after the bus write operation and will determine which data byte is returned by the LTC4156 during any operation www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 26 4156f subsequent bus read operations. the sub address pointer register is equivalent to the command code byte within the smbus write byte and read byte protocols explained in detail under the smbus protocol compatibility section. bus write operation the bus master initiates communication with the LTC4156 with a start condition and the LTC4156s write address. if the address matches that of the LTC4156, the LTC4156 returns an acknowledge . the bus master should then deliver the sub address. the sub address value is transferred to a special pointer register within the LTC4156 upon the return of the sub address acknowledge bit by the LTC4156. if the master wishes to continue the write transaction, it may then deliver the data byte. the data byte is transferred to an internal pending data register at the location of the sub address pointer when the LTC4156 acknowledges the data byte. the LTC4156 is then ready to receive a new sub address, optionally repeating the [sub address][ data ] cycle indefinitely. after the write address, the odd position bytes always represent a sub address pointer assignment and the even position bytes always represent data to be stored at the location referenced by the sub address pointer. the master may terminate communication with the LTC4156 after any even or odd number of bytes with either a repeat start or a stop condition. if a repeat start condition is initiated by the master, the LTC4156, or any other chip on the i 2 c bus, can then be addressed. the LTC4156 will remember, but not act on, the last input of valid data that it received at each sub address location. this cycle can also continue indefinitely. once all chips on the bus have been addressed and sent valid data, a global stop can be sent and the LTC4156 will immediately update all of its command registers with the most recent pending data that it had previously received. this delayed execution behavior is compliant with the pmbus group command protocol . bus read operation the LTC4156 contains seven readable registers. three are read only and contain status information. four contain control information which may be both written and read back by the bus master. only one of the seven sub addressed data registers is ac- cessible during each bus read operation . the data returned by the LTC4156 is from the data register pointed to by the contents of the sub address pointer register. the pointer register contents are determined by the most recent previ- ous bus write operation. in preparation for a bus read operation, it may be ad- vantageous for a bus master to prematurely terminate a write transaction with a stop or repeat start condition after transmitting only an odd number of bytes. the last transmitted byte then represents a pointer to the register of interest for the subsequent bus read operation. the bus master reads status data from the LTC4156 with a start or repeat start condition followed by the LTC4156 read address. if the read address matches that of the LTC4156, the LTC4156 returns an acknowledge. following the acknowledgement of its read address, the LTC4156 returns one bit of status information for each of the next eight clock cycles from the register selected by the sub address pointer. additional clock cycles from the master after the single data byte has been read will leave the sda line high (0xff transmitted). the LTC4156 will never acknowledge any bytes during a bus read operation with the exception of its read address. to read the same register again, the transaction may be repeated starting with a start followed by the LTC4156 read address. it is not necessary to rewrite the sub address pointer register if the sub address has not changed . to read a different register, a write transaction must be initiated with a start or repeat start followed by the LTC4156 write address and sub address pointer byte before the read transaction may be repeated. when the contents of the sub address pointer register point to a writeable command register, the data returned in a bus read operation is the pending command data at that location if it had been modified since the last stop condition. after a stop condition, all pending data is copied to the command registers for immediate effect. the contents of several writeable registers within the LTC4156 are modified upon removal of input power without an i 2 c transaction. usbilim[4:0] and wallilim [4:0] default to either 100ma mode (0x00) or clprog1 mode (0x1f) operation www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 27 4156f as explained in the alternate default input current limit section of operation. thus, the contents of these registers may be different from the last value written by the bus master, and reading back the contents may be useful to determine the state of the system. when the contents of the sub address pointer register point to a read-only status register, the data returned is a snapshot of the state of the LTC4156 at a particular instant in time. if no interrupt requests are pending, the status data is sampled when the LTC4156 acknowledges its read address, just before the LTC4156 begins data transmis- sion during a bus read operation. when an unmasked interrupt event takes place, the irq pin is driven low and data is latched in the three read-only status registers at that moment. any subsequent read operation from any status registers will return this frozen data to facilitate determination of the cause of the interrupt request. after the bus master clears the LTC4156 interrupt request, the status latches are cleared. bus read operations will then again return either a snapshot of the data at the read ad- dress acknowledge, or at the time of the next interrupt assertion, whichever comes first. smbus protocol compatibility the smbus specification is generally compatible with the i 2 c bus specification, but extends beyond i 2 c to define and standardize specific protocol formats for various types of transactions . the ltc 4156 i 2 c interface is fully compatible with four of the protocols defined by the smbus speci- fication. all control and status features of the LTC4156 can be accessed using the smbus protocols, although if high bus utilization is a concern, certain operations can be accomplished more efficiently by i 2 c bus operations that do not adhere to any of the smbus defined protocols. smbus write byte protocol 1 7 1 1 8 1 8 1 1 s slave address wr a command code a data byte a p the smbus write byte protocol can be used to modify the contents of any single control register in the LTC4156. the transaction is initiated by the bus master with a start condition. the smbus slave address corresponds to the LTC4156 write address, which is 0x09 when interpreted as a 7-bit word (0b 000 1001), followed by wr (value 0b0). the LTC4156 will acknowledge its write address. the smbus command code corresponds to the sub ad- dress pointer value and will be written to the sub address pointer register in the LTC4156. only the register loca- tions with write access (0x00 to 0x02, 0x06 to 0x07) are meaningful values for the sub address pointer when using this protocol. the LTC4156 will acknowledge the smbus command code byte. the smbus data byte corresponds to the command data to be written to the location pointed to by the sub address pointer register. the LTC4156 will acknowledge the smbus data byte. the stop condition at the end of the sequence will force an update to the command registers, causing the new command data to take immediate effect. smbus read byte protocol 1 7 1 1 8 1 1 7 1 1 8 1 1 s slave address wr a command code a sr slave address rd a data byte a p the smbus read byte protocol can be used to read the contents of any one of the seven control or status regis- ters with one bus transaction. the transaction is initiated by the bus master with a start condition. the smbus slave address corresponds to the LTC4156 write address, which is 0x09 when interpreted as a 7-bit word (0b 000 1001), followed by wr (value 0b0). the LTC4156 will acknowledge its write address. the smbus command code corresponds to the sub address pointer value and will be written to the sub address pointer register in the LTC4156. the LTC4156 will acknowledge the smbus command code byte. the master then issues a repeat start condition, followed by the LTC4156 slave address (0x09) and rd (0b1). the LTC4156 will acknowledge its read address. at this time the bus master becomes a receiver while continuing to clock scl. the LTC4156 becomes a slave transmitter and controls sda to place data on the bus. following the single data byte, the bus master has the option of transmitting either an ack or a nack bit. according to the i 2 c specification, a master operation www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 28 4156f must transmit a nack at the end of a read transaction to instruct the slave to terminate data transmission. because the LTC4156 terminates data transmission after one byte in all cases, whether the bus master transmits an ack or a nack is irrelevant. finally, a stop condition returns the bus to the idle state. smbus send byte protocol 1 7 1 1 8 1 1 s slave address wr a data byte a p the smbus send byte protocol can be used to modify the contents of the sub address pointer register without modifying the contents of any control registers. it has util- ity when preparing to later read status information from the LTC4156 using the smbus receive byte protocol. the transaction is initiated by the bus master with a start condition . the smbus slave address corresponds to the LTC4156 write address, which is 0x09 when interpreted as a 7-bit word (0b 000 1001) followed by wr (value 0b0). the LTC4156 will acknowledge its write address. the smbus data byte corresponds to the sub address pointer value and will be written to the sub address pointer register in the LTC4156. note that the data byte in this protocol is analogous to the command code in the write byte and read byte protocols. the LTC4156 will acknowledge the smbus data byte. finally, a stop condition returns the bus to the idle state. smbus receive byte protocol 1 7 1 1 8 1 1 s slave address rd a data byte a p the smbus receive byte protocol can be used to read the contents of the command or status register already selected by the sub address pointer register. this protocol is incapable of modifying the contents of the sub address pointer register, but may be useful to poll a single status register repeatedly with much less bus overhead than the other smbus protocols. the sub address pointer register can be modified by any of the smbus write byte, read byte or send byte protocols and the register contents will persist until they are modified again by one of these three protocols. the receive byte transaction is initiated by the bus mas- ter with a start condition. the smbus slave address corresponds to the LTC4156 read address, which is 0x09 when interpreted as a 7-bit word (0b 000 1001), followed by rd (value 0b1). the LTC4156 will acknowledge its read address. at this time the bus master becomes a receiver while continuing to clock scl. the LTC4156 becomes a slave transmitter and controls sda to place data on the bus. following the single data byte, the bus master has the option of transmitting either an ack or a nack bit. according to the i 2 c specification, a master must transmit a nack at the end of a read transaction to instruct the slave to terminate data transmission . because the LTC4156 terminates data transmission after one byte in all cases, whether the bus master transmits an ack or a nack is irrelevant. finally, a stop condition returns the bus to the idle state . programmable interrupt controller the LTC4156 can optionally generate active low, level- triggered interrupt requests on the irq pin in response to a number of status change or fault events. the three available bytes of status information are also frozen at the time the interrupt is triggered to aid in determining the cause of a transient interrupt. the contents of the four writeable command registers are never frozen by interrupts. the interrupt trigger events are grouped into six individually maskable categories corresponding to battery charger status, faults, input power detection, usb on - the - go , input current limit and input undervoltage cur - rent limit. the interrupt mask register (imr) is located at sub address location 0x06, with the six most significant bits representing the mask programming. refer to table ?3. table 4 lists the status triggers for each interrupt category . upon power - up , all interrupts default to disabled ( masked ). each interrupt category may be enabled by writing a 1 to the appropriate position in the imr. any data written to sub address 0x06 also has the side effect of clearing the pending interrupt upon the acknowledge bit of the data (third) byte. clearing the interrupt releases the irq pin and resumes status reporting of live data until the next interrupt. if no change to the interrupt mask is desired, the bus master must rewrite the previous data to sub address 0 x06 to clear an interrupt request. operation www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 29 4156f table 3. interrupt mask register interrupt mask register (imr) sub address 0 x 06 reg6 direction write/clear interrupt, read d7 d6 d5 d4 d3 d2 d1 d0 enable_charger_int 1 enable_fault_int 1 enable_ extpwr_ int 1 enable_otg_int 1 enable_at_ilim_int 1 enable_ input_ uvcl_ int 1 table 4. interrupt trigger sources mask category status triggers status registers enable_charger_int charger_ status[2:0] 0x03 enable_fault_int ovp_active bad_cell otg_ fault ntc_hot_ fault 0x03 0x04 enable_extpwr_int usbsns_good wallsns_good ext_pwr_good 0x04 enable_otg_int otg_enabled id_pin_detect 0x03 enable_at_ilim_int at_input_ilim 0x04 enable_input_uvcl_int input_uvcl_active 0x04 alternate default input current limit for usb compatible operation , connect both the clprog 1 and clprog2 pins to a single 1.21k 1% resistor, as shown in figure 5. when input power is applied, the LTC4156 will default to the 100ma input current limit mode. the i 2 c bus master may then subsequently change the input current limit to any of the other modes listed in table 8, where the 500ma and 900ma settings also cor - respond to usb compatible current limits. if input power is removed and reapplied , the ltc 4156 will once again default to 100ma mode until commanded to do otherwise by i 2 c. if the 100ma usb default current limit is insufficient for the application and usb compliance is not necessary , an alternate non-usb compliant default input current may be programmed with a second resistor on the clprog1 pin , as shown in figure 6. the resistor should be sized using the following equation: r clprog1 = 1.200v i vbuslim ? i vbusq ( ) ? 991 ( ) when input power is applied, the LTC4156 will default to the current limit set by the resistor connected to the clprog1 pin. the i 2 c bus master may then subsequently change the input current limit to any of the other modes listed in table 8, which require a second 1.21k program- ming resistor on the clprog2 pin. the i 2 c master may also change back to the default input current limit at any time by setting the appropriate usbilim or wallilim bits to the clprog1 mode. if input power is removed and reapplied at any time, the LTC4156 will again default to the clprog1 custom input current limit. the contents of usbilim[4:0] and wallilim [4:0] always contain the currently selected input current modes, which may be different from the data last written by the i 2 c bus master if input power was subsequently removed or was not present. the i 2 c bus master can read the above two registers at any time to determine the active input current limit mode. clprog2 clprog1 LTC4156 4156 f05 figure 5. usb default input current limit operation clprog2 clprog1 r2 r1 LTC4156 4156 f06 figure 6. non-usb default input current limit www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 30 4156f battery charger operation the LTC4156 contains a fully featured constant-current/ constant-voltage lifepo 4 battery charger with automatic recharge , bad cell detection , trickle charge , programmable safety timer, thermistor temperature qualified charging, programmable end-of-charge indication, programmable float voltage, programmable charge current, detailed i 2 c status reporting, and programmable interrupt generation. precharge/low battery when a battery charge cycle begins, the battery charger first determines if the battery is deeply discharged. if the battery voltage is below v lowbat , typically 2.7v, the LTC4156 will report the lowbat condition via i 2 c (see table 17). if the low battery voltage persists for more than one- half hour, the battery charger automatically terminates and indicates via the i 2 c port that the battery was unre- sponsive. when the battery voltage is low, charge current is reduced, both to protect the battery and to prevent ex- cessive power dissipation in the external pmos transistor. figure 1 shows the relationship between battery voltage and charge current reduction. when input power (usb or wall ) is unavailable, the i 2 c lowbat indication will always be true, independent of the actual state of charge of the battery and can be disregarded. constant-current when the battery voltage is above approximately 2.8v , the charger will attempt to deliver the programmed charge cur - rent in constant - current mode . depending on available input power and external load conditions, the battery charger may or may not be able to charge at the full programmed rate. the external load will always be prioritized over the battery charge current. likewise, the usb and wall input current limit programming will always be observed and only additional power will be available to charge the bat- tery . when system loads are light, battery charge current will be maximized. the upper limit of charge current is programmed by the combination of a resistor from prog to ground and the prog servo voltage value set in the i 2 c port . the maximum charge current will be given by the following expression: i charge = v prog r prog ? 1000 v prog can be set by the i 2 c port and ranges from 150mv to 1.2v in 75mv steps. the default value of v prog is 1.2v. v prog is controlled by bits icharge[3:0] located at sub address 0x02. see table 10. in either the constant - current or constant - voltage charging modes, the voltage at the prog pin will be proportional to the actual charge current delivered to the battery . the charge current can be determined at any time by monitoring the prog pin voltage and using the following relationship: i bat = v prog r prog ? 1000 recall, however, that in some cases the actual battery charge current, i bat , will be lower than the programmed current, i charge , due to limited input power available and prioritization of the system load drawn from v out . r prog should be set to match the capacity of the battery without regard to input power limitations. constant- voltage once the battery terminal voltage reaches the preset float voltage, the battery charger will hold the voltage steady and the charge current will decrease naturally toward zero. four voltage settings are available for final float voltage selection via the i 2 c port using bits vfloat [1:0] ( table 11). operation www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 31 4156f full capacity charge indication (c/x) since the prog pin always represents the actual charge current flowing, even in the constant-voltage phase of charging, the prog pin voltage represents the battery s state-of-charge during that phase. the LTC4156 has a full capacity charge indication comparator on the prog pin which reports its results via the i 2 c port. selection levels for the c/x comparator of 24mv, 60 mv, 120mv and 240mv are available by i 2 c control bits cxset[1:0] ( table 12). recall that the prog pin servo voltage can be programmed between 150mv to 1.2v. if the 1.2v servo setting represents the full-charge rate of the battery (1c), then the 120mv c/x setting would be equivalent to c/10. likewise, the 240mv c/x setting would represent c/5, the 24mv setting c/50 and the 60mv c/20. c/x indication is masked unless the battery charger is in constant-voltage mode to prevent false indication caused by limited input power. charge termination the battery charge cycle is terminated either at the expira- tion of a built - in programmable termination safety timer , or optionally at the full capacity charge indication ( c / x ). when the voltage on the battery reaches the user-programmed float voltage, the safety timer is started and the c/x com- parator is enabled. after the safety timer expires, charging of the battery will discontinue and no more current will be delivered. the safety timers default expiration time of one hour may be altered from one-fourth to four hours in four settings using the i 2 c bits timer[1:0] ( table 9). the four hour timer termination setting will also terminate the charge cycle before the expiration of the four hour timer when the battery charge current falls to the programmed full capacity (c/x) charge indication threshold. automatic recharge after the battery charger terminates, it will remain off, drawing only single microamperes of current from the battery . if the portable product remains in this state long enough, the battery will eventually self discharge. to en- sure that the battery is always topped off, a new charge cycle will automatically begin when the battery voltage falls below v rechrg (typically 97.6% of the programmed v float ). the termination safety timer will also reset back to zero. to prevent brief excursions below v rechrg from resetting the safety timer, the battery voltage must be below v rechrg for more than 2.5ms. a new charge cycle will also be initiated if input (usb or wall ) power is cycled or if the charger is momentarily disabled using the i 2 c port. the flow chart in figure 7 represents the battery chargers algorithm. ntc thermistor monitor the LTC4156 includes a 7-bit expanded scale analog to digital converter (adc) to monitor the battery temperature using an external negative temperature coefficient (ntc) thermistor placed close to the battery pack. to use this feature , connect the thermistor , r ntc , between the ntc pin and ground, and a bias resistor, r bias , between ntcbias and ntc, as shown in figure 8. r bias should be a 1% resistor with a value equal to the value of the chosen ntc thermistor at 25c (r 25 ). the thermistor measurement result is available via i 2 c port status reporting, except when the ship-and-store feature has been activated. when not in ship-and-store mode, the thermistor is automatically measured approximately every 2.4 seconds. the thermistor measurement result avail- able to the i 2 c port is updated at the end of each sample period. the low duty cycle of thermistor bias reduces operation www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 32 4156f operation figure 7. battery charger flow chart figure 8. standard thermistor network clear low battery and safety timers ntc out-of-range indicate ntc warning charge at constant current pause safety timer pause safety timer charge at fixed voltage run safety timer run low battery timer power available timer > 30 minutes safety timer expired v bat > 2.8v v bat < v rechrg i bat < c/x no no yes yes yes yes yes yes no no v bat > v float ? v bat < 2.7v 2.8v < v bat < v float ? no no no stop charging stop charging indicate battery fault v bat rising through v rechrg bat falling through v rechrg indicate charging stopped indicate constant voltage, i < c/x 4156 f07 no yes yes timer in 4 hour - c/x mode no yes v bat indicate constant current indicate constant voltage, i > c/x indicate low cell voltage trickle charge (8%) r ntc r bias LTC4156 4156 f08 ntc ntcbias t www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 33 4156f thermistor current, and its associated battery drain by a factor of 2000 from its dc value. a typical network using a 10k thermistor causes 115na of battery drain. a 100k thermistor would reduce this drain to 11.5na. to improve measurement resolution over the temperature range of interest, the full-scale range of the analog-to- digital converter is restricted to the range 0.113 to 0.895 ntcbias. the ntc adc result can be interpreted as follows: t r t r 25 = k span ? ntcval + k offset 1 ? k span ? ntcval ? k offset where ntcval is the decimal representation of the ntcval [6:0] status report in the range [0-127], adc con- stant k span = 0.006162, adc constant k offset = 0.1127, r t is the resistance of the thermistor at temperature t, and t is the resistance ratio of the thermistor at the two temperatures t and 25c. thermistor manufacturer data sheets will either provide a temperature lookup table relating t to t, or will supply a curve fit parameter b which can be used with the follow- ing equations to determine the thermistor temperature: t = b ln ( ) + b t 0 t = b ln k span ? ntcval + k offset 1 ? k span ? ntcval ? k offset ? ? ? ? ? ? + b t 0 where: t = temperature result expressed in kelvin t 0 = thermistor model nominal temperature, expressed in kelvin. typically 298.15k (25c + 273.15c) b = thermistor model material constant, expressed in kelvin. in addition to thermistor value reporting, the LTC4156 automatically pauses battery charging if the thermistor reading falls outside of limits corresponding to the range 0c to 60c for a vishay curve 2 thermistor . the ntc_too_cold and ntc_hot_ fault conditions are encoded in the i 2 c status report ntcstat [1:0]. charger _ status [2:0] will also report temperature warnings and faults when the battery charger is enabled. see table 13 and table 16. optionally, a charger status interrupt request may be generated when the thermistor reading enters or exits this temperature range. if the temperature reading is above a limit corresponding to 60c for a vishay curve 2 thermistor, an optional ntc_ hot_ fault interrupt may also be generated. the ntc_too_cold temperature indication is triggered when ntcval rises to decimal result 102. this corre- sponds to a cold, warning = 2.86 and 0c for a vishay curve 2 thermistor. the low temperature indication is cleared when the ntcval falls to decimal result 98. this corresponds to cold,reset = 2.53 and 2c for a vishay curve 2 thermistor. the ntc_hot_ fault temperature indication is triggered when ntcval falls to decimal result 19. this corre- sponds to critical, fault = 0.298 and 60c for a vishay curve 2 thermistor. the critically hot temperature indica- tion is cleared when ntcval rises to decimal result 23. this corresponds to critical,reset = 0.341 and 55.5c for a vishay curve 2 thermistor. it is possible to modify the thermistor bias network to adjust either one or both of the above temperature thresholds . see alternate ntc thermistors and biasing in the applications information section for implementation details. operation www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 34 4156f table 5. input undervoltage current limit control input undervoltage current limit control reg0 sub address 0x00 disable_input_uvcl direction write and readback disable_input_ uvcl d7 d6 d5 d4 d3 d2 d1 d0 enabled* 0 disabled 1 *default setting table 6. usb on-the-go id pin autonomous start-up usb on-the-go id pin autonomous start-up reg0 sub address 0x00 lockout_id_pin direction write and readback lockout_id_ pin d7 d6 d5 d4 d3 d2 d1 d0 autonomous start-up allowed* 0 autonomous start-up disabled 1 *default setting table 7. input current limit settings input current limit settings reg0, reg1 sub address 0x00 usb input current limit usbilim[4.0] sub address 0x01 wall input current limit wallilim[4:0] direction write and readback wallilim usbilim d7 d6 d5 d4 d3 d2 d1 d0 100ma max ( usb low power)* 0 0 0 0 0 500ma max (usb high power) 0 0 0 0 1 600ma max 0 0 0 1 0 700ma max 0 0 0 1 1 800ma max 0 0 1 0 0 900ma max (usb 3.0) 0 0 1 0 1 1000ma typical 0 0 1 1 0 1250ma typical 0 0 1 1 1 1500ma typical 0 1 0 0 0 1750ma typical 0 1 0 0 1 2000ma typical 0 1 0 1 0 2250ma typical 0 1 0 1 1 2500ma typical 0 1 1 0 0 2750ma typical 0 1 1 0 1 3000ma typical 0 1 1 1 0 2.5ma max (usb suspend) 0 1 1 1 1 select clprog1** 1 1 1 1 1 *default setting clprog1 and clprog2 shorted . automatically reset when input power is absent. **default setting two clprog resistors. automatically reset when input power is absent. operation www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 35 4156f table 8. input connector priority swap input connector priority swap reg1 sub address 0x01 priority direction write and readback priority d7 d6 d5 d4 d3 d2 d1 d0 wall input prioritized* 0 usb input prioritized 1 *default setting table 9. battery charger safety timer battery charger safety timer reg1 sub address 0x01 timer[1:0] direction write and readback timer[1:0] d7 d6 d5 d4 d3 d2 d1 d0 1 hr* 0 0 4 hr or c/x indication 0 1 0.25 hr 1 0 0.50 hr 1 1 *default setting. table 10. battery charger current limit battery charger current limit reg2 sub address 0 x 02 icharge[3.0] direction write and readback full- scale current (%) v prog servo (v) d7 d6 d5 d4 d3 d2 d1 d0 charger disabled 0.000 0 0 0 0 12.50 0.150 0 0 0 1 18.75 0.225 0 0 1 0 25.00 0.300 0 0 1 1 31.25 0.375 0 1 0 0 37.50 0.450 0 1 0 1 43.75 0.525 0 1 1 0 50.00 0.600 0 1 1 1 56.25 0.675 1 0 0 0 62.50 0.750 1 0 0 1 68.75 0.825 1 0 1 0 75.00 0.900 1 0 1 1 81.25 0.975 1 1 0 0 87.50 1.050 1 1 0 1 93.75 1.125 1 1 1 0 100.00* 1.200* 1 1 1 1 *default setting. operation www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 36 4156f table 11. battery charger float voltage battery charger float voltage reg2 sub address 0x02 vfloat [1:0] direction write and readback battery voltage (v) d7 d6 d5 d4 d3 d2 d1 d0 3.45* 0 0 3.55 0 1 3.60 1 0 3.80 1 1 *default setting. table 12. full capacity charge indication threshold full capacity charge indication threshold reg2 sub address 0 x 02 cxset[1:0] direction write and readback full- scale current (%) v prog threshold (v) d7 d6 d5 d4 d3 d2 d1 d0 10* 0.120* 0 0 20 0.240 0 1 2 0.024 1 0 5 0.060 1 1 *default setting. table 13. battery charger status report battery charger status report reg3 sub address 0x03 charger_ status[2:0] direction read battery charger status d7 d6 d5 d4 d3 d2 d1 d0 charger off 0 0 0 low battery voltage 0 0 1 constant current 0 1 0 constant voltage, vprog>vc/x 0 1 1 constant voltage, vprog LTC4156 37 4156f table 18. external power ( wall or usb) available external power ( wall or usb) available reg4 sub address 0x04 ext_pwr_good direction read power available status d7 d6 d5 d4 d3 d2 d1 d0 battery power only 0 external power available* 1 *never true when on-the-go step-up converter is active. table 19. usb input voltage valid usb input voltage valid reg4 sub address 0 x 04 usbsns_good direction read usbsns status d7 d6 d5 d4 d3 d2 d1 d0 usbsns voltage invalid 0 usbsns voltage valid * 1 *will be true with applied input voltage within valid range or on-the-go in regulation. table 20. wall input voltage valid wall input voltage valid reg4 sub address 0 x 04 wallsns_good direction read wallsns status d7 d6 d5 d4 d3 d2 d1 d0 wallsns voltage invalid 0 wallsns voltage valid 1 table 21. input current limit status input current limit status reg4 sub address 0 x 04 at_input_ilim direction read input current limit status d7 d6 d5 d4 d3 d2 d1 d0 input current limit inactive 0 input current limit active 1 table 22. input undervoltage current limit (brownout) status input undervoltage current limit (brownout) status reg4 sub address 0x04 input_uvcl_active direction read input undervoltage current limit status d7 d6 d5 d4 d3 d2 d1 d0 input uvcl inactive 0 input uvcl active 1 table 23. overvoltage protection fault overvoltage protection fault reg4 sub address 0 x 04 ovp_active direction read input overvoltage d7 d6 d5 d4 d3 d2 d1 d0 no fault 0 input (usb or wall) overvoltage 1 table 24. usb on-the-go step-up regulator fault shutdown usb on-the-go step-up regulator fault shutdown reg4 sub address 0x04 otg_ fault direction read step- up regulator status d7 d6 d5 d4 d3 d2 d1 d0 no fault 0 regulator over current shutdown 1 table 25. battery unresponsive to charging battery unresponsive to charging reg4 sub address 0 x 04 bad_cell direction read battery status d7 d6 d5 d4 d3 d2 d1 d0 no fault 0 low cell voltage timeout 1 operation www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 38 4156f table 26. ntc analog-to-digital converter result ntc analog-to- digital converter result reg5 sub address 0x05 ntcval [6:0] direction read ntc conversion result d7 d6 d5 d4 d3 d2 d1 d0 ntcval [6:0]* d d d d d d d see ntc thermistor monitor in operation section to convert adc result to temperature. table 27. ntc temperature out of range for battery charging ntc temperature out of range for battery charging reg5 sub address 0 x 05 ntc_ warning direction read ntc temp range d7 d6 d5 d4 d3 d2 d1 d0 temperature normal 0 too hot or too cold to charge 1 table 28. battery charger interrupt mask battery charger interrupt mask reg6 sub address 0x06 enable_charger_int direction write and readback interrupt enable status d7 d6 d5 d4 d3 d2 d1 d0 charger interrupts disabled* 0 charger interrupts enabled 1 *default. interrupt triggered by any change in charger_ status[2:0].any data written to sub address 0x06 has side effect of clearing any pending interrupt request. table 29. fault interrupt mask fault interrupt mask reg6 sub address 0 x 06 enable_fault_int direction write and readback interrupt enable status d7 d6 d5 d4 d3 d2 d1 d0 fault interrupts disabled* 0 fault interrupts enabled 1 *default. interrupt triggered by any change in ovp_active, bad_cell, otg_ fault or ntc_hot_ fault. any data written to sub address 0x06 has side effect of clearing any pending interrupt request. table 30. external power available interrupt mask external power available interrupt mask reg6 sub address 0x06 enable_extpwr_int direction write and readback interrupt enable status d7 d6 d5 d4 d3 d2 d1 d0 external power interrupts disabled* 0 external power interrupts enabled 1 *default. interrupt triggered by any change in usbsnsgd, wallsnsgd, or extpwrgd . any data written to sub address 0x06 has side effect of clearing any pending interrupt request. operation www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 39 4156f table 31. usb on-the-go interrupt mask usb on-the-go interrupt mask reg6 sub address 0 x 06 enable_otg_int direction write and readback interrupt enable status d7 d6 d5 d4 d3 d2 d1 d0 usb on-the-go interrupts disabled* 0 usb on-the-go interrupts enabled 1 *default. interrupt triggered by any change in en_boost, id_detect. any data written to sub address 0x06 has side effect of clearing any pending interrupt request. table 32. input current limit interrupt mask input current limit interrupt mask reg6 sub address 0x06 enable_at_ilim_int direction write and readback interrupt enable status d7 d6 d5 d4 d3 d2 d1 d0 input current limit interrupts disabled* 0 input current limit interrupts enabled 1 *default. interrupt triggered by any change in at_input_ilim. any data written to sub address 0x06 has side effect of clearing any pending interrupt request. operation table 33. input undervoltage current limit (brownout detection) interrupt mask input undervoltage current limit (brownout detection) interrupt mask reg6 sub address 0 x 06 enable_input_uvcl_int direction write and readback interrupt enable status d7 d6 d5 d4 d3 d2 d1 d0 input undervoltage current limit interrupts disabled* 0 input undervoltage current limit interrupts enabled 1 *default. interrupt triggered by any change in input_uvcl_active. any data written to sub address 0x06 has side effect of clearing any pending interrupt request. table 34. usb on-the-go step-up voltage converter manual activation usb on-the-go step-up voltage converter manual activation reg6 sub address 0x06 request_otg direction write and readback step-up regulator activation d7 d6 d5 d4 d3 d2 d1 d0 step-up regulator activation auto- matic or disabled* 0 enable step-up voltage regulator 1 *default. regulator cannot be activated if voltage is applied to either the usb or wall inputs. automatic activation controlled by lockout_id_pin. any data written to sub address 0x06 has side effect of clearing any pending interrupt request. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 40 4156f applications information alternate ntc thermistors and biasing the LTC4156 provides temperature qualified charging if a grounded thermistor and a bias resistor are connected to the ntc pin. charging is paused if the temperature rises above an ntc_hot_fault limit or falls below an ntc_too_ cold limit . by using a vishay curve 2 thermistor and a bias resistor whose value is equal to the room temperature resis - tance of the thermistor (r 25 ), the upper and lower tempera- tures are preprogrammed to approximately 60c and 0c, respectively. the ntc_hot_ fault threshold also optionally generates an interrupt. with minor modifications to the thermistor bias network as shown in figure 9, it is possible to adjust either one or both of the temperature thresholds with the constraint that it is usually not possible to move the temperature thresholds closer together. intuitively, this would require increased temperature sensitivity from the thermistor. too _ cold r too _ cold r 25 thermistor resistance ratio at desired ntc_ too_ cold threshold temperature relative to its reference temperature. hot _ fault r hot _ fault r 25 thermistor resistance ratio at desired ntc _ hot _ fault threshold temperature relative to its reference tem- perature. bias r bias r 25 ratio of low drift bias resistor to r 25 . temp _ range r temp _ range r 25 ratio of optional low drift dilution resistor to r 25 . note that r 25 , r t , r too _ cold and r hot _ fault and are all resistance values of the thermistor at different temperatures, while r bias and r temp_range are actual low drift resistors. in all of the following calculations, it will be necessary to determine the thermistors t at various temperatures. this parameter is dependent only upon the material prop- erties of the thermistor. t for a given thermistor and temperature may be found in one of two ways. thermistor manufacturers often provide a lookup table relating t to temperature in their data sheets. for any temperature t, t may be referenced directly. the second way to obtain t for any t requires the use of a modeling equation and a material constant specific to the thermistor: t = e b 1 t ? ? ? ? ? ? ? 1 t 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 9. alternate ntc bias network r ntc r bias LTC4156 4156 f09 ntc ntcbias t r temp_range in the explanation below, the following notation is used. r 25 ntc thermistor value at 25c. r bias low drift bias resistor, connected between the ntcbias and ntc pins. r temp_range optional dilution resistor, connected in series with the thermistor. t r t r 25 ther mistor resistance ratio at any temperature t relative to its reference temperature. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 41 4156f applications information where: e = natural logarithm base, approximately 2.71828 t = temperature of interest, expressed in kelvin t 0 = thermistor model nominal temperature, expressed in kelvin. typically 298.15k (25c + 273.15c) b = model material constant, expressed in kelvin. this model is a curve fit at t 0 and a second temperature. b is close to 4000k for most thermistors. higher b results in increased temperature sensitivity at the expense of reduced linearity over a wide temperature range simple alternate thermistor bias network by simply adjusting the bias resistor , r bias , and omitting the optional r temp_range , one of the temperature thresholds may be adjusted . the other temperature comparator threshold will be determined by the choice of the first temperature threshold and the ntcval thresholds fixed in the LTC4156. increasing r bias above r 25 shifts both temperature thresholds colder while simultaneously slightly compressing the temperature span between thresholds. likewise, decreasing r bias below r 25 shifts both temperature thresholds warmer while simultaneously slightly expanding the temperature span between thresholds. to program a single temperature threshold, obtain the value of either too_cold or hot_ fault for the chosen temperature threshold using one of the afore- mentioned methods and substitute into the appropriate following equation to calculate the value bias and then r bias . bias = 0.34917 ? too_cold bias = 3.35249 ? hot_ fault r bias = bias ? r 25 with bias for the newly programmed temperature threshold now determined, the other dependent tempera- ture threshold may be found by substituting bias into the remaining equation. the following equation may be used to convert any other ntc adc result ( ntcval) by substituting the k span and k offset values found in the electrical characteristics table. t = k span s ntcval + k offset 1 ? k span s ntcval ? k offset ? ? ? ? ? ? bias t may then be used to determine the temperature using either the lookup table provided by the thermistor manu- facturer or the curve fit model: t = b ln ( t ) + b t 0 advanced alternate thermistor bias network if an adjustment to r bias does not yield an acceptable span between temperature thresholds, a second low drift bias resistor may be added to the bias network between the ntc pin and the top of the thermistor. this resistor has the net effect of diluting the high thermal sensitivity of the thermistor with low drift resistance. the result is reduced thermal gain and a wider temperature span between the preprogrammed voltage thresholds of the LTC4156. using this additional resistor , both of the temperature comparator thresholds may be adjusted. after determining the t values for the two temperature thresholds of interest, the following equations may be used to determine bias and temp_range . temp_ range = 0.11626 ? too_ cold C 1.11626 ? hot_ fault r temp_range = temp_range ? r 25 bias = 0.38976 ? ( too_cold C hot_ fault ) r bias = bias ? r 25 it is possible to obtain a negative result for r temp_range which is not physically realizable using the previous equa- tions. a negative result indicates that the two chosen tem- perature thresholds are too close in temperature and require more thermal sensitivity than the thermistor can provide. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 42 4156f the generalized form of the ntc equations provided in the operations section are included above to facilitate interpretation of the thermistor analog to digital converter results using the custom bias network. if only r bias was modified, let temp_range = 0. choosing the input multiplexer/ overvoltage protection mosfets the LTC4156 contains an internal charge pump voltage doubler to drive n-channel mosfets via the usbgt and wallgt pins. the gate- source voltage available to drive the input multiplexer/protection fets is approximately equal to the input voltage, typically 4v to 6v. to ensure that the fet channels are sufficiently enhanced to provide a low resistance conduction path, the fet threshold volt- age should be less than approximately 2.5v. total gate leakage current should be below 1a to guarantee ample charge pump output voltage. the gate oxide breakdown voltage should be higher than 7v. the fet r ds(on) will negatively impact the switching regulator and battery charger efficiency at high current levels. with two protec- tion fets in series (mn1 and mn3, mn2 and mn4), the total resistance is the sum of the individual r ds(on) s. this combined resistance should be negligible compared to the typical 80m to 90m resistance of the LTC4156 internal switches for maximum performance . the drain breakdown voltage of devices mn1 and mn2 must be appropriate for the level of overvoltage protection desired. the drains will be exposed to the full magnitude of applied input voltage. the drains of devices mn3 and mn4 are exposed only to the operating voltage range of the LTC4156. therefore the drain breakdown voltage of devices mn3 and mn4 should be rated for at least 7v. table 35 lists several suit- able n-channel transistors. transistors with lower bv dss may be appropriate for devices mn3 and mn4 if reverse protection is not required. note that resistors r1 and r2 must also be sized appropriately for power dissipation based on the level of overvoltage protection desired, as explained in the operation section. table 35. recommended n-channel input multiplexer mosfets manufacturer part number r ds(on) (m) v t (v) bv dss (v) fairchild fdmc8651 4.3 1.1 30 fairchild fdmc8030 10.7 2.8 40 vishay si7938dp 5.6 2.5 40 applications information t = k span ? ntcval + k offset 1 ? k span ? ntcval ? k offset ? ? ? ? ? ? bias ? temp_ range t = b ln k span ? ntcval + k offset 1 ? k span ? ntcval ? k offset ? ? ? ? ? ? bias ? temp_ range ? ? ? ? ? ? + b t 0 figure 10. dual-input overvoltage protection v bus to usb input to wall input ovgcap usbgt usbsns wallgt LTC4156 wallsns 4156 f10 mn1 r1 r2 mn3 mn2 mn4 www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 43 4156f figure 11. single-input overvoltage protection figure 12. dual-input positive and negative voltage protection alternate input power configurations for applications requiring only a single input, the external circuit required for overvoltage protection is considerably simplified. only a single n-channel mosfet and resistor are required for positive voltage protection, as shown in figure 11, and ovgcap may be left unconnected. applica- tions using the usb on-the-go step-up regulator should connect r1 to usbsns and the gate of mn1 to usbgt. applications not using usb on-the-go may use either the usbsns / usbgt pins or the wallsns / wallgt pins. the unused pins may be left unconnected. for dual - input applications requiring reverse - voltage protection, no additional power transistors are required. the circuit in figure 12 provides positive protection up to the drain breakdown voltage rating of mn3 and mn4 and negative protection down to the drain breakdown volt- age rating of mn1 and mn2. q1 and q2 are small-signal transistors to protect the gate oxides of mn1 and mn2. note that it is necessary to orient the n-channel mosfets with the drain connections common and the source /body connections to the input connector and the v bus pin. choosing the inductor the LTC4156 is designed to operate with a 1h inductor, with core saturation, winding resistance, and thermal rise characteristics appropriate for the applications peak currents. the inductor current ripple magnitude is ap- proximately 400ma under normal conditions, resulting in a peak inductor current 200ma higher than the aver - age output current of the switching regulator. the aver - age output current of the step-down regulator is higher than the average input current by the ratio v bus / v out, neglecting efficiency losses. the LTC4156 can tolerate transient excursions beyond the inductor s core saturation level, but the inductor current will increase rapidly to the LTC4156s peak current clamp as incremental inductance tends toward zero. if an overload condition persists with a small inductor, it is possible that the inductor could be damaged by its own resistive temperature rise. applications information v bus to power input ovgcap usbgt usbsns wallgt LTC4156 wallsns 4156 f11 r1 mn1 v bus to usb input to wall input ovgcap usbgt usbsns wallgt LTC4156 wallsns 4156 f12 mn1 r5 47k r6 47k c1 opt 0.01f r3 5m r4 5m r1 3.6k r2 3.6k mn3 mn2 mn4 q1 q2 q3 q4 www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 44 4156f the inductor core should be made from a material such as ferrite , suitable for switching at 2.25 mhz without excessive hysteretic losses. table 36 lists several suitable inductors. table 36. recommended inductors manufacturer part number r dc ( m ) i max (a) package (mm) vishay ihlp2525ahe-b1romo1 17.5 7 6.5 6.9 3.2 coilcraft xfl4020-102me 10.8 5.4 4 4 2.1 tdk tdkltf 5022 t1r2n4r2- lf 21 4.2 5 5.2 2.2 i max is the lower of the typical 30% saturation current and self-heating current specifications. choosing the battery charger mosfets the LTC4156 requires a single external p-channel mos- fet connected between the chgsns and batsns pins to conduct battery charge and ideal diode currents. the threshold voltage magnitude should be less than approxi- mately 2.5 v . ( the p - channel threshold might be expressed as a negative number, v gs(th) , or as a positive number v sg(th) ). gate leakage current should be below 500na. drain voltage breakdown and gate oxide breakdown volt- ages should both be above 5v in magnitude. the LTC4156 contributes approximately 40m resistance in the current sense circuitry in series with the battery charger fet. channel resistance, r ds(on) , should be small relative to the 40m for maximum efficiency both charging the bat- tery and delivering power from the battery to the system load. table 37 lists several suitable p-channel transistors. optionally, a second p-channel mosfet may be con- nected in series with the first if the application requires that power be cut off from any downstream devices on v out in low power ship-and-store mode. further details about low power ship-and-store mode may be found in the operation section. the requirements for the second device are the same as those enumerated above, with the caveats that total gate leakage current is the sum of the individual leakage currents and total r ds(on) is the sum of the individual r ds(on) s. table 37. recommended p-channel battery charger mosfets manufacturer part number r ds(on) (m) v t (v) bv dss (v) fairchild fdmc510p 7.6 C0.5 C20 vishay si7123dn 11.2 C1 C20 vishay si5481du 24 C1 C20 v bus and v out bypass capacitors the style and value of the capacitors used with the ltc 4156 determine several important parameters such as regulator control loop stability and input voltage ripple. because the LTC4156 uses a step-down switching power supply from v bus to v out , its input current waveform contains high frequency components. it is strongly recommended that a low equivalent series resistance (esr) multilayer ceramic capacitor be used to bypass v bus . tantalum and aluminum capacitors are not recommended because of their high esr. the value of the capacitor on v bus directly controls the amount of input ripple for a given load current . increasing the size of this capacitor will reduce the input ripple. the usb specification allows a maximum of 10f to be connected directly across the usb power bus. if the overvoltage protection circuit is used to protect v bus , then its soft-starting nature can be exploited and a larger v bus capacitor can be used if desired. if one or both of the input channels are never used for usb, additional capacitance placed upstream of the overvoltage protection nmos de- vices can absorb significant high frequency current ripple. to prevent large v out voltage steps during transient load conditions , it is also recommended that a ceramic capacitor be used to bypass v out . the output capacitor is used in the compensation of the switching regulator. at least 22f with low esr are required on v out . additional capacitance will improve load transient performance and stability. applications information www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 45 4156f multilayer ceramic chip capacitors typically have excep- tional esr performance . mlccs combined with a tight board layout and an unbroken ground plane will yield very good performance and low emi emissions. the actual in- circuit capacitance of a ceramic capacitor should be measured with a small ac signal and dc bias, as is expected in- circuit. many vendors specify the capaci- tance versus voltage with a 1v rms ac test signal and, as a result, overstate the capacitance that the capacitor will present in the application. using similar operating condi- tions as the application, the user must measure, or request from the vendor, the actual capacitance to determine if the selected capacitor meets the minimum capacitance that the application requires. programming the input and battery charge current limits the LTC4156 features independent resistor programma- bility of the input current limit and battery charge current limit to facilitate optimal charging from a wide variety of input power sources . the battery charge current should be programmed based on the size of the battery and its associated safe charging rate. with the full-scale (default) charge current programmed with a resistor between prog and gnd, all other i 2 c selectable charge current settings are lower and may be appropriate for custom charge algorithms at extreme temperature or battery voltage. if the battery charge current limit requires more power than is available from the selected input current limit, the input current limit will be enforced and the battery will charge with less than the programmed current. thus, the battery charger should be programmed optimally for the battery without concern for the input source . resistive inputs and test equipment care must be exercised in the laboratory while evaluat- ing the LTC4156 with inline ammeters. the combined resistance of the internal current sense resistor and fuse of many meters can be 0.5 or more. at currents of 3a to 4a, it is possible to drop several volts across the meter, possibly resulting in unusual voltage readings or artificially high switch duty cycles. a resistive connection to the source of input power can be particularly troublesome. with the undervoltage cur - rent limit feature enabled, the switching regulator output power will be automatically reduced to prevent v bus from falling below 4.3v. this feature greatly improves tolerance of resistive input power sources (from either undersized wiring and connectors or test equipment) and facilitates stable behavior, but if engaged, it will result in much less power delivery to the system load and battery , depending on the magnitude of input resistance. if the undervoltage current limit feature is disabled and the input power source is resistive, the voltage will continue to fall through the falling undervoltage lockout threshold, eventually shutting down that input channel and resetting its input current limit back to the default setting. when the input voltage recovers, the channel will restart in the default current limit setting. applications information www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 46 4156f figure 13. higher frequency ground currents follow their incident path. slices in the ground plane cause high voltage and increased emissions board layout considerations the exposed pad on the backside of the LTC4156 package must be securely soldered to the pc board ground. this is the primary ground pin in the package, and it serves as the return path for both the control circuitry and the syn- chronous rectifier . furthermore, due to its high frequency switching circuitry , it is imperative that the input capacitor be as close to the LTC4156 as possible, and that there be an unbroken ground plane under the LTC4156 and its external input bypass capacitors. additionally, minimizing the area between the sw pin trace and inductor will limit high frequency radiated energy. the output capacitor carries the inductor ripple current. while not as critical as the input capacitor, an unbroken ground plane from this capacitors ground return to the inductor, input capacitor, and LTC4156 exposed pad will reduce output voltage ripple. high frequency currents, such as the input current on the LTC4156, tend to find their way on the ground plane along a mirror path directly beneath the incident path on the top of the board . if there are slits or cuts in the ground plane due to other traces on that layer, the current will be forced to go around the slits. if high frequency currents are not allowed to flow back through their natural least-area path, excessive voltage will build up and radiated emissions will occur (see figure 13). there should be a group of vias directly under the grounded backside leading directly down to an internal ground plane. to minimize parasitic inductance, the ground plane should be as close as pos- sible to the top plane of the pc board (layer 2). the batgate pin has limited drive current. care must be taken to minimize leakage to adjacent pc board traces, which may significantly compromise the 15mv ideal di- ode forward voltage. to minimize leakage, the trace can be guarded on the pc board by surrounding it with v out connected metal, which should generally be less than 1v higher than batgate. 4156 f13 applications information www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 47 4156f typical applications 7 11 8 4 3 1, 2, 28 3 10 5 6 29 12 18 4156 ta02 15 14 r3 499 c1 0.047f 9 23, 24, 25 r1 3.6k r2 1.21k l1: coilcraft xfl4020-102me mp1: vishay si5481du-t1-ge3 r4 100k 2.4a limit c2 22f to system load c3 10f to c to c wallsns sw wallgt v bus usbgt usbsns clprog1 clprog2 gnd prog v c id ntcbias 16 17 mp1 batsns batgate 19, 20 26, 27 l1 1h v outsns 13 v out 21, 22 chgsns LTC4156 i 2 c irq ovgcap ntc single input usb default current limit with minimum component count www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 48 4156f typical applications single input overvoltage protection with usb 100ma default input current limit and 5c/67c thermistor thresholds 7 11 8 4 3 1, 2, 28 3 10 5 6 29 12 18 4156 ta03 15 14 r3 665 c1 0.047f 9 23, 24, 25 r1 3.6k mn1 c3 10f r2 1.21k r4 8k c2 22f to system load to c to c wallsns sw wallgt v bus usbgt usbsns clprog1 clprog2 gnd prog v c id ntcbias 16 17 mp1 batsns batgate 19, 20 26, 27 l1 1h v outsns 13 v out 21, 22 chgsns LTC4156 i 2 c irq ovgcap ntc 1.8a limit l1: coilcraft xfl4020-102me mn1: si4430bdy mp1: vishay si5481du-t1-ge3 pack ntc: vishay ntcs0402e3103flt www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 49 4156f single input over/reverse voltage protection, usb default input current limit and C3c/66c thermistor thresholds 7 11 8 4 3 1, 2, 28 3 10 5 6 29 12 18 4156 ta04 15 14 r5 1k c1 0.047f 9 23, 24, 25 r1 5m r3 47k r4 3.6k mn1b c3 10f mn1a r4 1.21k r6 11.5k r7 1k c2 22f to system load to c to c wallsns sw wallgt v bus usbgt usbsns clprog1 clprog2 gnd prog v c id ntcbias 16 17 mp1 batsns batgate 19, 20 26, 27 l1 1h v outsns 13 v out 21, 22 chgsns LTC4156 i 2 c irq ovgcap ntc q1a q1b 1.2a limit l1: coilcraft xfl4020-102me mn1: fairchild fdmc8030 mp1: vishay si5481du-t1-ge3 pack ntc: vishay ntcs0402e3103flt q1: diodes/zetex mmdt3904-7-f typical applications www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 50 4156f dual input over/ undervoltage protection with 100ma usb default current limit typical applications 7 r2 3.6k r1 47k 11 8 4 3 1, 2, 28 3 10 5 6 29 12 18 4156 ta05 15 14 r8 499 c1 0.047f 9 23, 24, 25 r3 5m r4 5m r6 47k r5 3.6k mn1b mn2b c3 10f mn1a mn2a q1a q1b r7 1.21k r9 100k c2 22f to system load q2a q2b to c to c wallsns sw wallgt v bus usbgt usbsns clprog1 clprog2 gnd prog v c id ntcbias 16 17 mp1 batsns batgate 19, 20 26, 27 l1 1h v outsns 13 v out 21, 22 chgsns LTC4156 i 2 c irq ovgcap ntc 2.4a limit l1: coilcraft xfl4020-102me mn1, mn2: fairchild fdmc8030 mp1: vishay si5481du-t1-ge3 q1, q2: diodes/zetex mmdt3904-7-f www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 51 4156f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b) package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC4156 52 4156f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 0312 ? printed in usa related parts typical application dual input overvoltage protection with 1.21a default input current limit and output voltage disconnect 7 r1 3.6k 11 8 4 3 1, 2, 28 3 10 5 6 29 12 18 4156 ta06 15 14 r5 340 c2 0.047f c1 0.01f 9 23, 24, 25 r2 3.6k mn1b mn2b c4 10f mn1a mn2a r3 1k r4 1.21k r6 100k c3 22f to system load to c to c wallsns sw wallgt v bus usbgt usbsns clprog1 clprog2 gnd prog v c id ntcbias 16 17 mp2 batsns batgate 19, 20 26, 27 l1 1h v outsns 13 v out 21, 22 chgsns LTC4156 i 2 c irq ovgcap ntc mp1 l1: coilcraft xfl4020-102me mn1, mn2: fairchild fdmc8030 mp1, mp2: vishay, si5481du-t1-ge3 3.52a limit lifepo 4 battery part number description comments lt c 4155 dual input power manager/3.5a li-ion battery charger with i 2 c control and usb otg high efficiency 3.5a charger specifically designed for li-ion/polymer; monolithic switching regulator makes optimal use of limited power and thermal budget; float voltages: 4.05v , 4.10v , 4.15v , 4.20v ; i 2 c/smbus control and status feedback; 4mm w 5mm qfn-28 package. lt c 4085/ lt c 4085-1 linear usb power manager with ideal diode controller and li-ion charger charges single cell li-ion batteries directly from a usb port, thermal regulation, 200m ideal diode with <50m option, lt c 4085-1 has 4.1v v float , 3mm w 4mm dfn-14 package lt c 4088 high efficiency usb power manager and battery charger maximizes available power from usb port, bat- track?, instant-on operation, 1.5a max charge current, 3mm w 4mm dfn-14 package lt c 4089/ lt c 4089-1 lt c 4089 -5 high voltage usb power manager with ideal diode controller and high efficiency li-ion battery charger high efficiency 1.2a charger from 6v to 36v (40v max) input; bat- track adaptive output control ( lt c 4089); fixed 5v output ( lt c 4089-5/ lt c 4089-1); lt c 4089-1 for 4.1v float voltage batteries, 3mm w 6mm dfn-22 package; lt c 4090/ lt c 4090-5 high voltage usb power manager with ideal diode controller and high efficiency li-ion battery charger high efficiency 1.2a charger from 6v to 38v (60v max) input bat- track adaptive output control; lt c 4090-5 has no bat- track. 3mm w 6mm dfn-22 package lt c 4098/ lt c 4098-3.6 usb-compatible switchmode power manager with ovp lt c 4098-3.6 option for lifepo 4 cells; 66v ovp . 1.5a max charge current from wall, 600ma charge current from usb, 3mm w 4mm qfn-20 package lt c 4099 i 2 c controlled usb switchmode power manager with ovp 66v ovp . i 2 c for control and status readback, 1.5a max charge current from wall, 600ma charge current from usb, 3mm w 4mm qfn-20 package lt c 4160/ lt c 4160-1 switchmode power manager with ovp and usb-otg usb-otg 5v output, overvoltage protection, maximizes available power from usb port, bat- track, instant-on operation, 1.5a max charge current from wall, 600ma charge current from usb, 3mm w 4mm qfn-20 package www.datasheet.co.kr datasheet pdf - http://www..net/

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